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FS6128-07 Datasheet Preview

FS6128-07 Datasheet

PLL Clock Generator IC

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AMERICAN MICROSYSTEMS, INC.
FS6128-07
PLL Clock Generator IC with VCXO
August 2000
1.0 Features
Matches MK3727 center frequency characteristics
Phase-locked loop (PLL) device synthesizes output
clock frequency from crystal oscillator or external ref-
erence clock
On-chip tunable voltage-controlled crystal oscillator
(VCXO) allows precise system frequency tuning
3.3V supply voltage
Very low phase noise PLL
Use with “pullable” 14pF crystals – no external pad-
ding capacitors required
Small circuit board footprint (8-pin 0.150SOIC)
Custom frequency selections available - contact your
local AMI Sales Representative for more information
2.0 Description
The FS6128 is a monolithic CMOS clock generator IC
designed to minimize cost and component count in digital
video/audio systems.
At the core of the FS6128 is circuitry that implements a
voltage-controlled crystal oscillator (VCXO) when an ex-
ternal resonator (nominally 13.5MHz) is attached. The
VCXO allows device frequencies to be precisely adjusted
for use in systems that have frequency matching re-
quirements, such as digital satellite receivers.
A high-resolution phase-locked loop generates an output
clock (CLK) through a post-divider. The CLK frequency is
ratiometrically derived from the VCXO frequency. The
locking of the CLK frequency to other system reference
frequencies can eliminate unpredictable artifacts in video
systems and reduce electromagnetic interference (EMI)
due to frequency harmonic stacking.
Figure 1: Pin Configuration
XIN 1
VDD 2
XTUNE 3
VSS 4
8 XOUT
7 VSS
6 VDD
5 CLK
8-pin (0.150) SOIC
Table 1: Crystal / Output Frequencies
DEVICE
fXIN (MHz)
FS6128-07
13.500
NOTE: Contact AMI for custom PLL frequencies
CLK (MHz)
27.000
Figure 2: Block Diagram
XIN
XOUT
XTUNE
VCXO
PLL
DIVIDER
CLK
FS6128-07
American Microsystems, Inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ISO9001
8.8.00



AMI
AMI

FS6128-07 Datasheet Preview

FS6128-07 Datasheet

PLL Clock Generator IC

No Preview Available !

FS6128-07 pdf
FS6128-07
PLL Clock Generator IC with VCXO
AMERICAN MICROSYSTEMS, INC.
August 2000
Table 2: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN
TYPE
NAME
DESCRIPTION
1 AI XIN VCXO Feedback
2
P
VDD
Power Supply (+3.3V)
3
AI
XTUNE
VCXO Tune
4
P
VSS
Ground
5
DO
CLK
Clock Output
6
P
VDD
Power Supply (+3.3V)
7
DO
VSS
Ground
8
AO
XOUT
VCXO Drive
3.0 Functional Block Description
3.1 Voltage-Controlled Crystal
Oscillator (VCXO)
The VCXO provides a tunable, low-jitter frequency refer-
ence for the rest of the FS6128 system components.
Loading capacitance for the crystal is internal to the
FS6128. No external components (other than the reso-
nator itself) are required for operation of the VCXO.
Continuous fine-tuning of the VCXO frequency is accom-
plished by varying the voltage on the XTUNE pin. The
value of this voltage controls the effective capacitance
presented to the crystal. The actual amount that this load
capacitance change will alter the oscillator frequency de-
pends on the characteristics of the crystal as well as the
oscillator circuit itself.
It is important that the crystal load capacitance is speci-
fied correctly to “center” the tuning range. See Table 5.
A simple formula to obtain the “pulling” capability of a
crystal oscillator is:
f
(
ppm)
=
C1 × (C L2 C )L1 ×106
2 × (C0 + C L2)× (C0 + C )L1
where:
C0 = the shunt (or holder) capacitance of the crystal
C1 = the motional capacitance of the crystal
CL1 and CL2 = the two extremes (minimum and maximum)
of the applied load capacitance presented by the
FS6128.
EXAMPLE: A crystal with the following parameters is
used: C1 = 0.025pF and C0 = 6pF. Using the minimum
and maximum CL1 = 10pF, and CL2 = 20pF, the tuning
range (peak-to-peak) is:
f
=
0.025 × (20 10)×106
2 × (6 + 20)× (6 + 10)
= 300 ppm .
3.2 Phase-Locked Loop (PLL)
The on-chip PLL is a standard frequency- and phase-
locked loop architecture. The PLL multiplies the reference
oscillator frequency to the desired output frequency by a
ratio of integers. The frequency multiplication is exact
with a zero synthesis error (unless otherwise specified).
ISO9001
2
8.8.00


Part Number FS6128-07
Description PLL Clock Generator IC
Maker AMI
Total Page 7 Pages
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