memories that are accessed randomly with multiple
address lines and a parallel interface, the DataFlash uses a
serial interface to sequentially access its data. The simple
serial interface facilitates hardware layout, increases sys-
tem reliability, minimizes switching noise, and reduces
package size and active pin count. The device is optimized
for use in many commercial and industrial applications
where high density, low pin count, low voltage, and low
power are essential. Typical applications for the DataFlash
are digital voice storage, image storage, and data storage.
The device operates at clock frequencies up to 15 MHz
with a typical active read current consumption of 15 mA.
To allow for simple in-system reprogrammability, the
AT45D081A does not require high input voltages for pro-
gramming. The device operates from a single power
supply, 4.5V to 5.5V, for both the program and read opera-
tions. The AT45D081A is enabled through the chip select
pin (CS) and accessed via a three-wire interface consisting
of the Serial Input (SI), Serial Output (SO), and the Serial
All programming cycles are self-timed, and no separate
erase cycle is required before programming.
WP FLASH MEMORY ARRAY
PAGE (264 BYTES)
BUFFER 1 (264 BYTES)
BUFFER 2 (264 BYTES)
To provide optimal flexibility, the memory array of the
AT45D081A is divided into three levels of granularity com-
prised of sectors, blocks and pages. The Memory Architec-
ture Diagram illustrates the breakdown of each level and
details the number of pages per sector and block. All pro-
gram operations to the DataFlash occur on a page by page
basis; however, the optional erase operations can be per-
formed at the block or page level.