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Atmel Electronic Components Datasheet

TS8308500 Datasheet

ADC 8-bit 500 Msps

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Main Features
8-bit Resolution
500 Msps (min) Sampling Rate
Power Consumption: 3.8W Typ
500 mVpp Differential or Single-ended Analog Inputs
Differential or Single-ended 50ECL Compatible Clock Inputs
ECL or LVDS/HSTL Output Compatibility
ADC Gain Adjust
Data Ready Output with Asynchronous Reset
Gray or Binary Selectable Output Data; NRZ Output Mode
Enhanced CBGA Package with Ceramic Lid
Evaluation Board: TSEV8308500GL (Detailed Specification on Request)
Demultiplexer TS81102G0: Companion Device Available
Performance
1.3 GHz Full Power Input Bandwidth
Band Flatness: 0.5 dB up to 500 MHz
SINAD = 45 dB (7.2 Effective Bits), SFDR = 54 dBc
at FS = 500 Msps, FIN = 20 MHz
SINAD = 43 dB (7.1 Effective Bits), SFDR = 53 dBc
at FS = 500 Msps, FIN = 250 MHz
SINAD = 42 dB (7.0 Effective Bits), SFDR = 52 dBc
at FS = 500 Msps, FIN = 500 MHz (-3 dB FS)
2-tone IMD: TBD (199.5 MHz, 200.5 MHz) at 500 Msps
DNL = ±0.3 LSB INL = ±0.7 LSB
Low Bit Error Rate (10-13) at 500 Msps, Tj = 90°C
ADC 8-bit
500 Msps
TS8308500
Applications
• Digital Sampling Oscilloscopes
• Satellite Receiver
• Electronic Countermeasures/Electronic Warfare
• Direct RF Down-conversion
Screening
• Atmel Standard Screening Level
• Temperature Range:
– 0°C < Tc; Tj < +90°C
– -40°C < Tc ; Tj < + 110°C
Description
The TS8308500 is a monolithic 8-bit analog-to-digital converter, designed for digitizing
wide bandwidth analog signals at very high sampling rates of up to 500 Msps.
The TS8308500 is using an innovative architecture, including an on-chip Sample and
Hold (S/H), and is fabricated with an advanced high-speed bipolar process.
The on-chip S/H has a 1.3 GHz full power input bandwidth, providing excellent
dynamic performance in undersampling applications (High IF digitizing).
Rev. 2193A–BDC–046/03
1


Atmel Electronic Components Datasheet

TS8308500 Datasheet

ADC 8-bit 500 Msps

No Preview Available !

TS8308500 pdf
Functional
Description
Block Diagram
Figure 1. Simplified Block Diagram
GAIN
VIN, VINB
Master/Slave Track & Hold Amplifier
Resistor
Chain
Analog
Encoding
Block
4
4
Interpolation
Stages
5
CLK, CLKB
Clock
Buffer
DRRB DR, DRB
GORB
Regeneration
Latches
45
Error Correction &
Decode Logic
8
Output Latches &
Buffers
8
DATA, DATAB OR, ORB
Functional
Description
The TS8308500 is an 8-bit 500 Msps ADC based on an advanced high-speed bipolar technol-
ogy featuring a cutoff frequency of 25 GHz.
The TS8308500 includes a front-end master/slave Track and Hold stage (S/H), followed by an
analog encoding stage and interpolation circuitry.
Successive banks of latches are regenerating the analog residues into logical data before
entering an error correction circuitry and a resynchronization stage followed by 75differential
output buffers.
The TS8308500 works in fully differential mode from analog inputs up to digital outputs.
The TS8308500 features a full-power input bandwidth of 1.3 GHz.
Control pin GORB is provided to select either the Gray or Binary data output format.
The gain control pin is provided in order to adjust the ADC gain.
A Data Ready output asynchronous reset (DRRB) is available on TS8308500.
The TS8308500 uses only vertical isolated NPN transistors together with oxide isolated poly-
silicon resistors, which allow enhanced radiation tolerance (no performance drift measured at
150 kRad total dose).
2 TS8308500
2193A–BDC–04/03


Part Number TS8308500
Description ADC 8-bit 500 Msps
Maker ATMEL Corporation
Total Page 30 Pages
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