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Agere Systems
Agere Systems

TMXA84622 Datasheet Preview

TMXA84622 Datasheet

Ultramapper Full Transport

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TMXA84622 pdf
Hardware Design Guide, Revision 1
February 21, 2003
TMXA84622 Ultramapper Full Transport
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
www.datasheet4u.com
1 Introduction
The last issue of this data sheet was November 27, 2002. A change history (since the last issue) is included in Section 12
Change History, on page 55. Red change bars have been installed on all text, figures, and tables that were added or
changed. All changes to the text are highlighted in red. Changes within figures, and the figure title itself, are highlighted in
red, if feasible. Formatting or grammatical changes have not been highlighted. Deleted sections, paragraphs, figures, or
tables will be specifically mentioned.
The documentation package for the TMXA84622 Full Transport 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1 sys-
tem chip consists of the following documents:
s The Register Description and the System Design Guide. These documents are available on a password-protected web-
site.
s The Ultramapper Full Transport Product Description and the Ultramapper Full Transport Hardware Design Guide (this
document). These documents are available on the public website shown below (select Mappers/MUXes):
http://www.agere.com/enterprise_metro_access/index.html
This document describes the hardware interfaces to the Agere Systems TMXA84622 Ultramapper Full Transport device.
Information relevant to the use of the device in a board design is covered. Pin descriptions, dc electrical characteristics,
timing diagrams, ac timing parameters, packaging, and operating conditions are included.
If the reader saves this document to disk and displays it using Acrobat ®Reader ®, clicking on any blue text will bring the
reader to that reference point. Clicking on the back arrow (Go to previous View) in the toolbar of the Acrobat Reader will
bring the reader back to the starting point.
To contact Agere Systems, see the last page of this document or contact your Agere representative.
622/155 Mbits/s SONET/SDH
ADM Front End
LOPOH
DS3/E3/DS2/DS1/E1 PDH
Tributary Termination
6
High-Speed IF
622 Mb/STS-12/STM-4
155 Mb/STS-3/STM-1
Clock and Data
8
CDR
Clock/Sync
TMUX
6
Protection Link
622 Mb/STS-12/STM-4
155 Mb/STS-3/STM-1
Clock and Data
8
STS-12/
STM-4/
STS-3/
STM-1
CDR
STSPP
S
T
S
X
C
Miscellaneous
24
JTAG
MPU
MCDR
5
JTAG IF
49 12
MPU IF
(x3)
STS-3/STM-1 Mate
Interconnect
LOPOH
FRM (X3)
x28/x21
DS1/J1/E1
CG
5 PLL IF
SPEMPR
(x3)
(3-5)
SPEMPR
(x3)
(0-2)
STS-1
LT
(x3)
TPG/TPM
(x3)
x28/x21
VTMPR
(x3) (x3)
E13 M13
MUX MUX
MRXC
DS1/J1/E1
VT/TU
DS2/E2
DS3/E3
3
1
3
1
X3
x28/x21
DS1/E1
DJA
x6
DS3/E3
DJA
System Interfaces
42 (x6) DS3/E3
(x3) STS-1
(x3) NSMI
24 (x3) STS-1
(Total of 3 STS-1 Max)
344
Low-Speed I/O
Transport Modes
4DS1/J1/E1 (x86): x84/x63 + prot.
4DS2/E2 (X86): x63/x36 + prot.
11
E2, DS2,
VC12 VC11
AIS Clocks
66
Power and GND pins not shown
22
TOAC POAC
DS1XCLK,
E1XCLK
DS3XCLK,
E3XCLK
10/10/02 Full Transport
Figure 1-1. Ultramapper Full Transport Block Diagram and High-Level Interface Definition



Agere Systems
Agere Systems

TMXA84622 Datasheet Preview

TMXA84622 Datasheet

Ultramapper Full Transport

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TMXA84622 pdf
TMXA84622 Ultramapper Full Transport
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
Hardware Design Guide, Revision 1
February 21, 2003
Table of Contents
Contents
Page
1 Introduction ........................................................................................................................................................................1
2 Pin Information ...................................................................................................................................................................6
www.22d..a12taBPshaienlel AtD4suisa.cigogmrnammen..t..M...a..t.r..ix..................................................................................................................................................................................................................................................................................................1. 76
2.3 Pin Types ...................................................................................................................................................................20
2.4 Pin Definitions ............................................................................................................................................................21
3 Absolute Maximum Ratings .............................................................................................................................................32
3.1 Handling Precautions ................................................................................................................................................32
4 Electrical Characteristics .................................................................................................................................................33
4.1 Recommended Operating Voltages ..........................................................................................................................33
4.2 Recommended Powerup Sequence ..........................................................................................................................33
4.3 Power Consumption ..................................................................................................................................................33
4.4 ac and dc Characteristics ..........................................................................................................................................34
4.4.1 LVCMOS Interface Characteristics ..................................................................................................................34
4.4.2 LVDS Interface Characteristics ........................................................................................................................35
5 Timing ..............................................................................................................................................................................36
5.1 TMUX High-Speed Interface Timing ..........................................................................................................................36
5.2 THSSYNC Characteristics .........................................................................................................................................37
5.3 STS-3/STM-1 Mate Interconnect Timing ...................................................................................................................38
5.4 TOAC, POAC, and LOPOH Timing ...........................................................................................................................39
5.5 DS3/E3/STS-1 Timing ...............................................................................................................................................40
5.6 NSMI Timing ..............................................................................................................................................................41
5.7 Shared Low-Speed Line Timing ................................................................................................................................41
6 Reference Clocks ............................................................................................................................................................42
7 Microprocessor Interface Timing .....................................................................................................................................47
7.1 Synchronous Write Mode ..........................................................................................................................................47
7.2 Synchronous Read Mode ..........................................................................................................................................48
7.3 Asynchronous Write Mode ........................................................................................................................................50
7.4 Asynchronous Read Mode ........................................................................................................................................51
8 Other Timing ....................................................................................................................................................................53
9 Hardware Design File References ...................................................................................................................................53
10 909-Pin PBGA Diagram .................................................................................................................................................54
11 Ordering Information ......................................................................................................................................................55
12 Change History ...............................................................................................................................................................55
13 Glossary .........................................................................................................................................................................56
2 Agere Systems Inc.


Part Number TMXA84622
Description Ultramapper Full Transport
Maker Agere Systems
Total Page 30 Pages
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