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Agere Systems
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TMXF28155 Datasheet Preview

TMXF28155 Datasheet

TMXF28155 Super Mapper 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

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TMXF28155 pdf
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
1 Features
s Versatile IC supports 155/51 Mbits/s SONET/SDH
interface solutions for T3/E3, DS2, T1/E1/J1, and
DS0/E0/J0 applications.
s Implementation supports both linear (1 + 1, unpro-
tected) and ring (UPSR) network topologies.
s Provides full termination of up to 21 E1, 28 T1, or
28 J1.
s Low power 3.3 V supply.
s –40 °C to +85 °C industrial temperature range.
s 456-pin ball grid array (PBGA) package.
s Complies with Bellcore*, ITU, ANSI , ETSI and Jap-
anese TTC standards: GR-253-CORE, GR-499,
(ATT) TR-62411, ITU-T G.707, G.704, G.706, G.783,
G.962, G.964, G.965, Q.542, T1.105, JT-G704,
JT-G706, JT-G707, JT-I431-a, ETS 300 417-1-1,
ETS 300 011, T1.107, T1.404.
1.1 SONET/SDH Interface
s Termination of a single 155 Mbits/s STS-3/STM-1 or
single 51 Mbits/s STS-1/STM-0.
s Built-in clock and data recovery circuit at
155 Mbits/s STS-3/STM-1 interface (can be dese-
lected if external clock recovery is provided).
s Supports overhead processing for all transport and
path overhead bytes.
s Optional insertion and extraction of overhead bytes
via a serial transport overhead access channel. Con-
figurable as dedicated DCC channels.
s Software controlled linear 1 + 1 protection via dedi-
cated interface to protection card.
s Full path termination and SPE extraction/insertion.
s SONET/SDH compliant condition and alarm report-
ing.
s Built-in diagnostic loopback modes.
s 8 kHz line frame sync output.
* Bellcore is now Telcordia Technologies. Telcordia Technologies is a
trademark of Telcordia Technologies, Inc.
ANSI is a registered trademark of American National Standards
Institute, Inc.
1.2 STS/STM Pointer Interpreter
s Interprets STS/AU/TU-3 pointers.
s Synchronizes 8 kHz frame and 2 kHz superframe to
system/shelf timing reference by setting the transmit
STS-3/STM-1 pointers to a fixed value of 522.
s Monitors/terminates SPE path overhead.
1.3 Telecom Bus Interface
s Telecom bus interface to mate devices including
clock, data[8], parity, SPE-, J0-, J1-, and V1 timing
indicator.
s Line and path RDI and REI signals passed to mate
devices.
s Three Super Mapper devices, two configured as
mate devices, provide full termination of an
STS-3/STM-1. A three-chip solution to terminate
84 DS1s/J1s or 63 E1s.
1.4 VT Termination/Generation (x28/x21)
s Monitors/terminates VT path overhead for
28 VT1.5/TU-11 or 21 VT2/TU-12.
s Synchronizes VT/TU SPE to system/shelf timing ref-
erence by setting the transmit VT/TU pointers to fixed
values for asynchronous mapping or by dynamically
changing the transmit VT/TU pointers for byte syn-
chronous mapping.
s Fixed pointer generation in transmit side for asyn-
chronous mapping.
s Dynamic pointer generation in transmit side for byte-
synchronous mapping.
1.5 Mapping/Multiplexing Modes (x28/x21)
s Maps DS3 clear channel or framed signal into STS-1
or TUG-3.
s Maps T1/E1/J1 into VT/TU (including DS1 into
TU-12).
s Supports asynchronous, byte-synchronous, and bit-
synchronous mapping.



Agere Systems
Agere Systems

TMXF28155 Datasheet Preview

TMXF28155 Datasheet

TMXF28155 Super Mapper 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

No Preview Available !

TMXF28155 pdf
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
1 Features (continued)
s Supports UPSR applications via the dedicated ring
interface and an external tributary selector.
s Supports all valid T1/E1/J1 multiplexing structures
into STS-1 and STS-3/STM-1:
STS-3/STS-1/SPE/VTG/VTx
STM-1/AU-3/TUG-2/TU-1x/VC-1x
STM-1/AU-4/TUG-3/TUG-2/TU-1x/VC-1x
s Allows grooming of VTs/TUs in granularity of TUG-2s
within the STS-3/STM-1 signal.
s Supports J2 trace identifier monitoring/insertion.
s Configurable VT/TU slot selection for DS1, E1, and
J1 insertion and drop.
s Automatic receive monitor functions include VT/TU
RDI-V, REI-V, BIP-2 errors, AIS-V, LOP-V.
s Complies with GR-253-CORE, GR-499, ITU-T
G.707, G.704, G.783, T1.105, JT-G707, ETS 300
417-1-1.
1.6 M13 Features
s Sources may be broadcast, looped back, or routed
to/from a test-pattern generator or monitor.
s Any DS1 or E1 channel may be routed through the
jitter attenuator.
s DS3 may be configured for the M13 to interconnect
with the SPE, or external I/O to interconnect with the
M13 or SPE.
1.8 Jitter Attenuation
s PLL-free receive operation using built-in digital jitter
attenuator (in VT/VC mode or M13 mode).
s Configurable to meet jitter and MTIE requirements.
1.9 PDH Interfaces
s One DS3, 7x DS2.
s x28/x21 framed or unframed DS1 or E1 interfaces.
s One additional dedicated protection channel for
DS2/DS1/E1.
s Configurable multiplexer/demultiplexer for 28 DS1
signals, 21 E1 signals, or 7 DS2 signals to/from a
DS3 signal.
s Operates in either M23 or C-bit parity mode.
s Provisionable time slot selection for DS1, E1, and
DS2 insertion or drop.
s Full alarm monitoring and generation (LOS, BPV,
EXZ, OOF, SEF, AIS, RAI, FEAC, P-bit and C-bit par-
ity errors, FEBE).
s HDLC transmitter with 128-byte data buffer and
HDLC receiver with 128-byte data FIFO for the C-bit
parity path maintenance data link.
s DS3, DS2, DS1, and E1 loopback and loopback
request generation.
s Complies with T1.102, T1.107, T1.231, T1.403,
T1.404, GR 499, G.747, and G.775.
1.7 DS3/DS2/DS1/E1 Cross Connect
s Highly configurable interconnect for up to 28 DS1 or
21 E1 signals to/from the framer, external pins, M13,
or VT mappers.
s Supports up to seven DS2 signals to/from the exter-
nal pins or M13.
1.10 T1/E1/J1 Framing Features (x28/x21)
s x28/x21 T1/E1/J1 channels.
s Line coding: B8ZS, HDB3, ZCS, AMI, and
CMI (JJ20-11).
s T1 framing modes: ESF, D4, SLC ®-96, T1 DM DDS,
and SF (Ft only).
s E1 framing: G.704 basic and CRC-4 multiframe con-
sistent with G.706.
s J1 framing modes: JESF (Japan).
s Supports T1 and E1 unframed and transparent trans-
mission format.
s T1 signaling modes: transparent;
register and system access for ESF 2-state, 4-state,
and 16-state; D4 2-state, 4-state, and 16-state;
SLC-96 2-state, 4-state, and 16-state; J-ESF han-
dling groups maintenance and signaling; VT 1.5
SPE 2, 4, 16 state.
s E1 signaling modes: transparent;
register and system access for entire TS16 multi-
frame structure as per ITU G.732.
s Signaling debounce and change of state interrupt.
s V5.2 Sa7 processing.
2 Agere Systems Inc.


Part Number TMXF28155
Description TMXF28155 Super Mapper 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Maker Agere Systems
Total Page 30 Pages
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