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Alliance Semiconductor Corporation
Alliance Semiconductor Corporation

ASM3P2508SP Datasheet Preview

ASM3P2508SP Datasheet

Clock Synthesizer and Frequency Generator

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ASM3P2508SP pdf
February 2005
ASM3P2508SP
wrewwv.D0a.t4aSheet4U.com
Clock Synthesizer and Frequency Generator with Peak EMI reduction
Features
ƒ Dual PLL based Architecture
ƒ Operates with a 3.3V ±0.3V supply.
ƒ Generates an EMI optimized Spread Spectrum
PCI Clock output
ƒ Generates a high accuracy non Spread T1 clock of
±25ppm accuracy.
ƒ Generates a non spread system reference clock
ƒ Low power CMOS design.
ƒ Input frequency: 25 MHz.
ƒ Outputs:
Sys_ REF_CLK: 20 MHz
T1 Clock: 25 MHz (±25 ppm)
PCI_CLK: 33.33MHz Spread Spectrum
ƒ Frequency deviation: -0.5% (Typ).
ƒ Available in 8L SOIC Package.
Product Description
The ASM3P2508SP is a versatile Dual PLL based Clock
Synthesizer and Frequency Generator optimised and
designed specifically for three clock frequencies. The
PCI_CLK output from ASM3P2508SP reduces
electromagnetic interference (EMI) at the clock source,
allowing system wide reduction of EMI of all clock
dependent signals. ASM3P2508SP allows significant
system cost savings by reducing the number of circuit
board layers, ferrite beads & shielding that are
traditionally required to pass EMI regulations.
Block Diagram
PWRDNB
The ASM3P2508SP uses the most efficient and
optimized modulation profile approved by the FCC.
ASM3P2508SP modulates the output of a PLL in order to
“spread” the bandwidth of a synthesized clock, and more
importantly, decreases the peak amplitudes of its
harmonics. This results in a significantly lower system
EMI compared to the typical narrow band signal produced
by oscillators and most frequency generators. Lowering
EMI by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation’ (SSCG).
In addition to the SSCG output, ASM3P2508SP
generates two high accuracy clock signals -
T1 Clock @ 25.00MHz with +/- 25ppm stability, and a
20MHz Sys_ REF_CLK.
Applications
The ASM3P2508SP is targeted towards Consumer,
Industrial, Data and Telecommunications applications.
Key Specifications
Description
Supply voltages
Input Frequency
Cycle-to-Cycle Jitter
Output Duty Cycle
Output Rise and Fall Time
SSC Modulation Rate
SSC Frequency Deviation
Specification
VDD = 3.3V ±0.3V
25 MHz
175 pS ( Max)
45/55%
1.1 nS (Max)
30KHz (Typ)
-0.5% (Typ)
VDD
T1_CLK
XIN/CLKIN
XOUT
Osc
Input
Divider
PLL 1
PLL 2
Modulation
Output
Divider
Output
Divider
Sys_REF_CLK
PCI_CLK
VSS
Alliance Semiconductor
2575, Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
Notice: The information in this document is subject to change without notice.



Alliance Semiconductor Corporation
Alliance Semiconductor Corporation

ASM3P2508SP Datasheet Preview

ASM3P2508SP Datasheet

Clock Synthesizer and Frequency Generator

No Preview Available !

ASM3P2508SP pdf
February 2005
ASM3P2508SP
rwewvw.0D.a4taSheet4U.com
Pin Configuration
XIN/CLKIN 1
8 T1_CLK
XOUT 2
VDD 3
7
ASM3P2508SP
6
VSS
PCI_CLK
Sys_REF_CLK 4
5 PWRDNB
Pin Description
Pin#
1
2
3
4
5
6
7
8
Pin Name
XIN/CLKIN
XOUT
VDD
Sys_REF_CLK
PWRDNB
PCI_CLK
VSS
T1_CLK
Type
I
O
P
O
I
O
P
O
Description
Crystal connection or external reference frequency input. This pin has dual functions.
It can be connected either to an external crystal or an external reference clock.
Crystal connection. If using an external reference, this pin must be left unconnected.
Power supply for the entire chip
PLL 1 output System Reference Clock @ 20MHz
Power-down control pin. Pull low to enable power-down mode. Connect to VDD if not
used. Power -down Mode shuts off all the Outputs.
PLL 2 Spread spectrum clock output @ 33.33MHz
Ground to entire chip. Connect to system ground
Reference output T1 Clock @ 25MHz
Typical Modulation Profile
Absolute Maximum Ratings
Symbol
Parameter
Rating
Unit
VDD, VIN
TSTG
TA
Ts
TJ
Voltage on any pin with respect to Ground
Storage temperature
Operating temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
-0.5 to +7.0
-65 to +125
0 to 70
260
150
V
°C
°C
°C
°C
TDV
Static Discharge Voltage
(As per JEDEC STD 22- A114-B)
2 KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Clock Synthesizer and Frequency Generator with Peak EMI reduction
Notice: The information in this document is subject to change without notice.
2 of 7


Part Number ASM3P2508SP
Description Clock Synthesizer and Frequency Generator
Maker Alliance Semiconductor Corporation
Total Page 7 Pages
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