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Alliance Semiconductor Corporation
Alliance Semiconductor Corporation

ASM3P623S00B Datasheet Preview

ASM3P623S00B Datasheet

Zero Cycle Slip Peak EMI reduction IC

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ASM3P623S00B pdf
July 2005
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ASM3P623S00A/B/C/D/E/F
Zero Cycle Slip Peak EMI reduction IC
General Features
ƒ Input frequency range: 20MHz - 50MHz.
ƒ Zero input - output propagation delay.
ƒ Low-skew outputs.
ƒ Output-output skew less than 250pS.
ƒ Device-device skew less than 700pS.
ƒ Less than 200pS cycle-to-cycle jitter is compatible
with Pentium® based systems.
ƒ Available in 16pin, 150mil SOIC, 4.4mm TSSOP
(ASM3P623S00D/E/F), and in 8pin, 150 mil SOIC,
4.4mm TSSOP Packages (ASM3P623S00A/B/C).
ƒ 3.3V operation
ƒ Advanced 0.35µ CMOS technology.
ƒ The First True Drop-in Solution.
Functional Description
ASM3P623S00D/E/F is a versatile, 3.3V zero-delay buffer
designed to distribute high-speed clocks. It accepts one
reference input and drives out eight low-skew clocks. It is
available in a 16pin package. The ASM3P623S00A/B/C is
the eight-pin version of the ASM3P623S00. It accepts one
reference input and drives out one low-skew clock.
All parts have on-chip PLLs that lock to an input clock on
the CLKIN pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad, internal to the device.
Multiple ASM3P623S00D/E/F devices can accept the same
input clock and distribute it. In this case, the skew between
the outputs of the two devices is guaranteed to be less than
700pS.
All outputs have less than 200pS of cycle-to-cycle jitter.
The input and output propagation delay is guaranteed to be
less than 250pS, and the output-to-output skew is
guaranteed to be less than 250pS.
Please refer Differential Cycle Slips and Spread Spectrum
Control Table” for deviations and differential Cycle Slips
for ASM3P623S00A/B/C and the ASM3P623S00D/E/F
devices
The ASM3P623S00A/B/C and the ASM3P623S00D/E/F
are available in two different configurations, as shown in
the ordering information table.
Block Diagram
VDD SSON SS%
CLKIN
Reference
Divider
Feedback
Divider
Modulation
Phase
Detector
Loop
Filter
PLL
VCO
Feedforward
Divider
CLKOUT
VSS
Alliance Semiconductor
2575 Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
Notice: The information in this document is subject to change without notice.



Alliance Semiconductor Corporation
Alliance Semiconductor Corporation

ASM3P623S00B Datasheet Preview

ASM3P623S00B Datasheet

Zero Cycle Slip Peak EMI reduction IC

No Preview Available !

ASM3P623S00B pdf
July 2005
wrewvw.D1a.0taSheet4U.com
Spread Spectrum Frequency Generation
The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the
edge rates also get faster. Analysis shows that a square
wave is composed of fundamental frequency and
harmonics. The fundamental frequency and harmonics
generate the energy peaks that become the source of
EMI. Regulatory agencies test electronic equipment by
measuring the amount of peak energy radiated from the
equipment. In fact, the peak level allowed decreases as
the frequency increases. The standard methods of
reducing EMI are to use shielding, filtering, multi-layer
Cycle Slip
Cycle slip occurs when the output clock edge
‘wanders’ away from the corresponding input clock
edge. There are two types of cycle slips – a Differential
cycle slip and an Integral cycle slip. The differential
cycle slip is caused due the clock edge variation over
one modulation cycle. It is defined by the maximum
amount of ‘wander’ the clock edge will have within one
Pin Configuration
ASM3P623S00A/B/C/D/E/F
PCBs etc. These methods are expensive. Spread
spectrum clocking reduces the peak energy by reducing
the Q factor of the clock. This is done by slowly
modulating the clock frequency. The ASM3P623S00X
uses the center modulation spread spectrum technique in
which the modulated output frequency varies above and
below the reference frequency with a specified
modulation rate. With center modulation, the average
frequency is the same as the unmodulated frequency and
there is no performance degradation
modulation cycle. Integral cycle slip occurs due to the
accumulation of the cycle slip over successive modulation
cycles. In ASM3P623S00A/B/C/D/E/F the differential cycle
slip is within the value mentioned in the Differential Cycle
Slip and Spread Spectrum Control Table” and the Integral
Cycle Slip is ‘Zero’.
CLKIN
NC
SS%
GND
18
2 ASM3P623S00A/B/C 7
36
45
NC
VDD
CLKOUT
SSON
CLKIN 1
16 CLKOUT8
CLKOUT1 2
15 CLKOUT7
VDD 3
14 CLKOUT6
SS% 4 ASM3P623S00 D/E/F 13 VDD
GND 5
12 GND
CLKOUT2 6
11 CLKOUT5
CLKOUT3 7
10 CLKOUT4
DLY CNTRL 8
9 SSON
Zero Cycle Slip Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
2 of 16


Part Number ASM3P623S00B
Description Zero Cycle Slip Peak EMI reduction IC
Maker Alliance Semiconductor Corporation
Total Page 16 Pages
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