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Arizona Microtek
Arizona Microtek

AZ100LVEL16VV Datasheet Preview

AZ100LVEL16VV Datasheet

Dual Frequency ECL/PECL Oscillator Gain Stage & Buffer

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AZ100LVEL16VV pdf
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ARIZONA MICROTEK, INC.
AZ100LVEL16VV
Dual Frequency ECL/PECL Oscillator Gain Stage & Buffer with Enable
FEATURES
PACKAGE AVAILABILITY
High Bandwidth for 1GHz
Similar Operation as AZ100EL16VR
except with selectable data input pairs
Operating Range of 3.0V to 5.5V
Minimizes External Components
Available in a 3x3mm MLP Package
S–Parameter (.s2p) and IBIS Model
Files Available on Arizona
Microtek Website
PACKAGE
PART NUMBER MARKING NOTES
MLP 16 (3x3) RoHS
AZM+
Compliant / Lead (Pb) AZ100LVEL16VVL+ 16K
1,2
Free <Date Code>
DIE
AZ100LVEL16VVXP N/A
3
1 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape
& Reel.
2 Date code format: “Y” for year followed by “WW” for week.
3 Waffle Pack
DESCRIPTION
The AZ100LVEL16VV is a specialized oscillator gain stage with two selectable data input pairs and a high gain
output buffer including an enable. The QHG/Q¯ HG outputs have a voltage gain several times greater than the Q/Q¯
outputs.
The AZ100LVEL16VV provides two selectable data input pairs that permit switching between two different
oscillator frequencies. When the select pin (SEL) is LOW or open (NC) data from the D0/D¯¯0 is selected. When the
SEL pin is HIGH data from the D1/D¯¯1 is selected. Allowing continuous oscillator operation, the (EN) enable works
with either data input pair. When EN is HIGH or open (NC), input data is passed to both sets of outputs. When EN
is LOW, the QHG/Q¯ HG outputs will be forced LOW/HIGH respectively, while input data will continue to be passed to
the Q/Q¯ outputs. The EN and SEL inputs can be driven with an ECL/PECL signal or a full supply swing CMOS
type logic signal.
The AZ100LVEL16VV also provides a VBB with a 1.5mA sink/source current. Each data input is separately
connected to VBB with a 470Ω internal bias resistor. Bypassing VBB to ground with a 0.01 μF capacitor is
recommended.
Each Q/Q¯ output has a 4 mA on-chip pull-down current source. External resistors may also be used to increase
pull-down current of the Q/Q¯ to a maximum of 25mA each (includes a 4 mA on-chip current source).
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
1630 S. STAPLEY DR., SUITE 127 MESA, ARIZONA 85204 USA (480) 962-5881 FAX (480) 890-2541
www.azmicrotek.com



Arizona Microtek
Arizona Microtek

AZ100LVEL16VV Datasheet Preview

AZ100LVEL16VV Datasheet

Dual Frequency ECL/PECL Oscillator Gain Stage & Buffer

No Preview Available !

AZ100LVEL16VV pdf
AZ100LVEL16VV
PIN DESCRIPTION
PIN
D0/D¯¯0, D1/D¯¯1
Q/Q¯
QHG/Q¯ HG
VBB
SEL
EN
VCC
VEE
FUNCTION
Data Inputs
Data Outputs
Data Outputs w/High Gain
Reference Voltage Output
Selects Data Inputs
Enable Input
Positive Supply
Negative Supply
Q
Q
D0
D0
D1
D1
EN
High/
Open
High/
Open
Low
Low
SEL
Low/
Open
High
Low/
Open
High
TRUTH TABLE
Q Q¯ QHG
D0/D¯¯0 D0/D¯¯0 D0/D¯¯0
D1/D¯¯1 D1/D¯¯1 D1/D¯¯1
D0/D¯¯0 D0/D¯¯0 Low
D1/D¯¯1 D1/D¯¯1 Low
HG
D0/D¯¯0
D1/D¯¯1
High
High
VBB
SEL
470
4mA EA.
EN
QHG
QHG
VEE
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol
Characteristic
Rating
VCC PECL Power Supply (VEE = 0V)
VI PECL Input Voltage (VEE = 0V)
VD/D¯ PECL D/D¯ Input Voltage (VEE = 0V)
VEE ECL Power Supply (VCC = 0V)
VI ECL Input Voltage (VCC = 0V)
VD/D¯ ECL D/D¯ Input Voltage
(VCC = 0V)
Output Current --- Continuous Q/Q¯
IOUT
--- Surge
Q/Q¯
--- Continuous QHG/Q¯ HG
--- Surge
QHG/Q¯ HG
TA Operating Temperature Range
TSTG Storage Temperature Range
0 to +6.0
0 to +6.0
±0.75 with respect to VBB
-6.0 to 0
-6.0 to 0
±0.75 with respect to VBB
25
50
50
100
-40 to +85
-65 to +150
1. This voltage is the difference between each input pin (D/D¯ ) and VBB.
100K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = GND)
Symbol
Characteristic
-40°C
Min Max
0°C
Min Max
25°C
Min Max
VOH Output HIGH Voltage1
VOL Output LOW Voltage1
-1045
-1925
-835
-1555
-1025
-1900
-835
-1620
-1025
-1900
-835
-1620
Input HIGH Voltage
VIH D/D¯ -1165 -740 -1165 -740 -1165 -740
EN, SEL -1165 VCC -1165 VCC -1165 VCC
Input LOW Voltage
VIL
D/D¯ -1900
-1475
-1900
-1475
-1900
-1475
EN, SEL
VEE
-1475
VEE
-1475
VEE
-1475
VBB Reference Voltage
-1390
-1250
-1390
-1250
-1390
-1250
IIL
Input LOW Current EN/SEL
-100
-100
-100
IIH Input HIGH Current EN/SEL
150
150
150
IEE Power Supply Current1
47 47 47
1. Specified with Q/Q¯ open and each QHG/Q¯ HG output terminated through a 50Ω resistor to VCC-2V.
Unit
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
mA
°C
°C
85°C
Min Max
-1025
-835
-1900
-1620
-1165
-1165
-1900
VEE
-1390
-100
-740
VCC
-1475
-1475
-1250
150
51
Unit
mV
mV
mV
mV
mV
μA
μA
mA
April 2007 * REV - 9
www.azmicrotek.com
2


Part Number AZ100LVEL16VV
Description Dual Frequency ECL/PECL Oscillator Gain Stage & Buffer
Maker Arizona Microtek
Total Page 9 Pages
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