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Cypress Semiconductor Electronic Components Datasheet

CY62157EV30 Datasheet

8-Mbit (512 K x 16) Static RAM

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CY62157EV30 pdf
CY62157EV30 MoBL®
8-Mbit (512 K × 16) Static RAM
8-Mbit (512 K × 16) Static RAM
Features
Thin small outline package (TSOP) I package configurable as
512 K × 16 or 1 M × 8 static RAM (SRAM)
High speed: 45 ns
Temperature ranges
Industrial: –40 °C to +85 °C
Automotive-A: –40 °C to +85 °C
Automotive-E: –40 °C to +125 °C
Wide voltage range: 2.20 V to 3.60 V
Pin compatible with CY62157DV30
Ultra low standby power
Typical standby current: 2 A
Maximum standby current: 8 A (Industrial)
Ultra low active power
Typical active current: 1.8 mA at f = 1 MHz
Easy memory expansion with CE1, CE2, and OE features
Automatic power down when deselected
Complementary Metal Oxide Semiconductor (CMOS) for
optimum speed and power
Available in Pb-free and non Pb-free 48-ball very fine-pitch ball
grid array (VFBGA), Pb-free 44-pin TSOP II and 48-pin TSOP I
packages
Functional Description
The CY62157EV30 is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life(MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Place the device
into standby mode when deselected (CE1 HIGH or CE2 LOW or
both BHE and BLE are HIGH). The input or output pins (I/O0
through I/O15) are placed in a high impedance state when the
device is deselected (CE1HIGH or CE2 LOW), the outputs are
disabled (OE HIGH), Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH), or a write operation is active (CE1
LOW, CE2 HIGH and WE LOW).
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is
written into the location specified on the address pins (A0 through
A18). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written into the location specified on the
address pins (A0 through A18).
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See Truth Table on page 13
for a complete description of read and write modes.
Logic Block Diagram
AA190
A
A
A
8
7
6
A5
A4
A3
A
A
A
2
1
0
DATA IN DRIVERS
512 K × 16/1 M x 8
RAM Array
I/O0–I/O7
I/O8–I/O15
Power Down
Circuit
COLUMN DECODER
CE2
CE1
BHE
BLE
BYTE
BHE
WE
OE
BLE
CE2
CE1
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4#U: .3n8et-05445 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 30, 2011
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Cypress Semiconductor Electronic Components Datasheet

CY62157EV30 Datasheet

8-Mbit (512 K x 16) Static RAM

No Preview Available !

CY62157EV30 pdf
CY62157EV30 MoBL®
Contents
Pin Configuration .............................................................3
Product Portfolio ..............................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
Data Retention Characteristics .......................................6
Data Retention Waveform ................................................6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Read Cycle No. 1 (Address Transition Controlled) .....8
Read Cycle No. 2 (OE Controlled) ..............................8
Write Cycle No. 1 (WE Controlled) ..............................9
Write Cycle No. 2 (CE1 or CE2 Controlled) ..............10
Write Cycle No. 4
(BHE/BLE Controlled, OE LOW) ......................................12
Truth Table ......................................................................13
Ordering Information ......................................................14
Ordering Code Definitions .........................................14
Package Diagrams ..........................................................15
Acronyms ........................................................................18
Document Conventions .................................................18
Units of Measure .......................................................18
Document History Page .................................................19
Sales, Solutions, and Legal Information ......................21
Worldwide Sales and Design Support .......................21
Products ....................................................................21
PSoC Solutions .........................................................21
Document #: 38-05445 Rev. *I
Page 2 of 21
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Part Number CY62157EV30
Description 8-Mbit (512 K x 16) Static RAM
Maker Cypress Semiconductor
Total Page 21 Pages
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