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Cypress Semiconductor Electronic Components Datasheet

CY62177DV20 Datasheet

32-Mbit (2M x 16) Static RAM

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CY62177DV20 pdf
CY62177DV20 MoBL2™
32-Mbit (2M x 16) Static RAM
Features
Very high speed: 70 ns
Wide voltage range: 1.7V – 2.2V
Ultra low active power
Typical active current: 2 mA at f = 1 MHz
Typical active current: 12 mA at f = fMAX
Ultra low standby power
Easy memory expansion with CE1, CE2, and OE features
Automatic power down when deselected
CMOS for optimum speed and power
Offered in 48-ball VFBGA package
Functional Description
The CY62177DV20 is a high performance CMOS static RAM
organized as 2M words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life(MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that reduces power consumption
by 99% when addresses are not toggling. The device can also
be put into standby mode when deselected (CE1 HIGH or CE2
LOW or both BHE and BLE are HIGH). The input and output pins
(IO0 through IO15) are placed in a high impedance state when:
the device is deselected (CE1HIGH or CE2 LOW); outputs are
disabled (OE HIGH); both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH); when a write operation
is in progress (CE1 LOW, CE2 HIGH and WE LOW).
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO0 through IO7) is written
into the location specified on the address pins (A0 through A20).
If Byte High Enable (BHE) is LOW, then data from IO pins (IO8
through IO15) is written into the location specified on the address
pins (A0 through A20).
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from
memory appears on IO8 to IO15. See the Truth Table on page 9
for a complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DATA IN DRIVERS
2M × 16
RAM ARRAY
IO0–IO7
IO8–IO15
COLUMN DECODER
Power Down
Circuit
CE2
CE1
BHE
BLE
BHE
WE
OE
BLE
CE2
CE1
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocatuamSheenett4#U:.0ne0t1-44018 Rev. **
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 08, 2008
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Cypress Semiconductor Electronic Components Datasheet

CY62177DV20 Datasheet

32-Mbit (2M x 16) Static RAM

No Preview Available !

CY62177DV20 pdf
Pin Configuration
CY62177DV20 MoBL2™
Figure 1. 48-Ball VFBGA (8 x 9.5 x 1.2 mm) Top View [1]
12 34 56
BLE OE A0 A1 A2 CE2
IO8 BHE A3 A4 CE1 IO 0
IO 9 IO 10 A5 A6 IO 1 IO 2
VSS IO11 A17 A7
IO3 Vcc
VCC IO 12 DNU A16 IO 4 Vss
IO 14 IO 13 A14 A15 IO 5 IO 6
IO 15 A19 A12 A13 WE IO 7
A18 A8 A9 A10 A11 A20
A
B
C
D
E
F
G
H
Product Portfolio
Product
CY62177DV20LL
VCC Range (V)
Min Typ[2] Max
1.7 1.8 2.2
Speed
(ns)
70
Power Dissipation
Operating ICC (mA)
f = 1 MHz
Typ[2]
Max
f = fmax
Typ[2]
Max
Standby ISB2 (μA)
Typ[2]
Max
2 4 12 25 5 50
Notes
1. DNU pins must be connected to VSS or left open.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
Document #: 001-44018 Rev. **
Page 2 of 11
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Part Number CY62177DV20
Description 32-Mbit (2M x 16) Static RAM
Maker Cypress Semiconductor
Total Page 11 Pages
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