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Cypress Semiconductor Electronic Components Datasheet

CY62187EV30 Datasheet

64-Mbit (4 M x 16) Static RAM

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CY62187EV30 pdf
CY62187EV30 MoBL®
64-Mbit (4 M × 16) Static RAM
64-Mbit (4 M × 16) Static RAM
Features
Very high speed
55 ns
Wide voltage range
2.2 V to 3.7 V
Ultra low standby power
Typical standby current: 8 μA
Maximum standby current: 48 μA
Ultra low active power
Typical active current: 7.5 mA at f = 1 MHz
Easy memory expansion with CE1, CE2, and OE features
Automatic power down when deselected
CMOS for optimum speed and power
Available in Pb-free 48-ball FBGA package
Functional Description
The CY62187EV30 is a high performance CMOS static RAM
organized as 4 M words by 16-bits. This device features
advanced circuit design to provide ultra low active current. It is
ideal for providing More Battery Life(MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption by 99 percent when addresses are not toggling.
The device can also be put into standby mode when deselected
(CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The
input and output pins (I/O0 through I/O15) are placed in a high
impedance state when: deselected (CE1HIGH or CE2 LOW),
outputs are disabled (OE HIGH), both Byte High Enable and Byte
Low Enable are disabled (BHE, BLE HIGH), or during a write
operation (CE1 LOW, CE2 HIGH and WE LOW).
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0 through
A21). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written into the location specified on the
address pins (A0 through A21).
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See the Truth Table on page
9 for a complete description of read and write modes.
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4NUu.nmebt er: 001-48998 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 14, 2011
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Cypress Semiconductor Electronic Components Datasheet

CY62187EV30 Datasheet

64-Mbit (4 M x 16) Static RAM

No Preview Available !

CY62187EV30 pdf
Logic Block Diagram
A10
A9
A8
A7
A6
A5
A4
A3
A2
A
A
1
0
DATA-IN DRIVERS
4096K × 16
RAM Array
COLUMN DECODER
Power down
Circuit
CY62187EV30 MoBL®
I/O0–I/O7
I/O8–I/O15
BHE
WE
OE
BLE
CE2
CE1
Document Number: 001-48998 Rev. *F
Page 2 of 15
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Part Number CY62187EV30
Description 64-Mbit (4 M x 16) Static RAM
Maker Cypress Semiconductor
Total Page 15 Pages
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