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Cypress Semiconductor Electronic Components Datasheet

CY8C21323 Datasheet

(CY8C21x23) Mixed Signal Array

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CY8C21123, CY8C21223, CY8C21323
PSoC® Mixed Signal Array
Features
Powerful Harvard Architecture Processor
M8C Processor Speeds to 24 MHz
Low power at High Speed
2.4V to 5.25V Operating Voltage
Operating Voltages down to 1.0V using On-Chip Switch
Mode Pump (SMP)
Industrial Temperature Range: -40°C to +85°C
Advanced Peripherals (PSoC Blocks)
Four Analog Type “E” PSoC Blocks Provide:
• Two Comparators with DAC Refs
• Single or Dual 8-Bit 8:1 ADC
Four Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
Full Duplex UART, SPIMaster or Slave
• Connectable to All GPIO Pins
Complex Peripherals by Combining Blocks
Flexible On-Chip Memory
4K Flash Program Storage 50,000 Erase/Write Cycles
256 Bytes SRAM Data Storage
In-System Serial Programming (ISSP)
Partial Flash Updates
Flexible Protection Modes
EEPROM Emulation in Flash
Complete Development Tools
Free Development Software (PSoC Designer)
Full Featured, In-Circuit Emulator and Programmer
Full Speed Emulation
Complex Breakpoint Structure
128 Bytes Trace Memory
Precision, Programmable Clocking
Internal ±2.5% 24/48 MHz Oscillator
Internal Oscillator for Watchdog and Sleep
Programmable Pin Configurations
25 mA Drive on All GPIO
Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
Up to Eight Analog Inputs on GPIO
Configurable Interrupt on all GPIO
Additional System Resources
I2C™ Master, Slave and MultiMaster to 400 kHz
Watchdog and Sleep Timers
User Configurable Low Voltage Detection
Integrated Supervisory Circuit
On-Chip Precision Voltage Reference
Logic Block Diagram
PSoC
CORE
SystemBus
Port 1 Port 0
Global Digital Interconnect
Global Analog Interconnect
SRAM
Interrupt
Controller
SROM
Flash
CPU Cor e
(M8C)
Sleep and
Watchdog
Clock Sources
(Includes IMO and ILO)
DIGITAL SYSTEM
Digital
PSoC Block
Array
ANALOG SYSTEM
Analog
PSoC Block
Array
Analog
Ref .
Digital
Clocks
POR and LVD
Sw itch
I2C Mode
System Resets
Pu mp
SYSTEM RESOURCES
Internal
Voltage
Ref .
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-12022 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 22, 2008
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Cypress Semiconductor Electronic Components Datasheet

CY8C21323 Datasheet

(CY8C21x23) Mixed Signal Array

No Preview Available !

CY8C21323 pdf
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CY8C21123, CY8C21223, CY8C21323
PSoC® Functional Overview
The PSoC® family consists of many Mixed Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components with
a low cost single-chip programmable component. A PSoC
device includes configurable blocks of analog and digital logic,
and programmable interconnect. This architecture allows the
user to create customized peripheral configurations, to match
the requirements of each individual application. Additionally, a
fast CPU, Flash program memory, SRAM data memory, and
configurable IO are included in a range of convenient pinouts.
The PSoC architecture, as shown in Figure 1, consists of four
main areas: the Core, the System Resources, the Digital
System, and the Analog System. Configurable global bus
resources allow the combining of all device resources into a
complete custom system. Each PSoC device includes four digital
blocks. Depending on the PSoC package, up to two analog
comparators and up to 16 general purpose IO (GPIO) are also
included. The GPIO provide access to the global digital and
analog interconnects.
PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a four MIPS 8-bit Harvard
architecture microprocessor.
System Resources provide additional capability, such as digital
clocks to increase the flexibility of the PSoC mixed-signal arrays,
I2C functionality for implementing an I2C master, slave, Multi-
Master, an internal voltage reference that provides an absolute
value of 1.3V to a number of PSoC subsystems, a switch mode
pump (SMP) that generates normal operating voltages off a
single battery cell, and various system resets supported by the
M8C.
The Digital System consists of an array of digital PSoC blocks,
which can be configured into any number of digital peripherals.
The digital blocks can be connected to the GPIO through a series
of global bus that can route any signal to any pin. This frees
designs from the constraints of a fixed peripheral controller.
The Analog System consists of four analog PSoC blocks,
supporting comparators and analog-to-digital conversion up to 8
bits in precision.
Digital System
The Digital System consists of four digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references. Digital peripheral
configurations include:
PWMs (8 to 32 bit)
PWMs with Dead band (8 to 32 bit)
Counters (8 to 32 bit)
Timers (8 to 32 bit)
UART 8 bit with selectable parity (up to four)
SPI master and slave
I2C slave, master, MultiMaster (one available as a System
Resource)
Cyclical Redundancy Checker/Generator (8 to 32 bit)
IrDA (up to four)
Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global bus that can route any signal to any pin. The
busses also allow for signal multiplexing and performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This provides an optimum
choice of system resources for your application. Family
resources are shown in Table 1 on page 3.
Figure 1. Digital System Block Diagram
Port 1
Port 0
8
8
DigitalClocks To SystemBus
FromCore
ToAnalog
System
DIGITAL SYSTEM
Digital PSoCBlockArray
Row 0
4
DBB00 DBB01 DCB02 DCB03
4
8
8
GIE[7:0]
GIO[7:0]
Gl o b al Di g i tal
Interconnect
GOE[7:0]
GOO[7:0]
Document Number: 38-12022 Rev. *H
Page 2 of 37
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Part Number CY8C21323
Description (CY8C21x23) Mixed Signal Array
Maker Cypress Semiconductor
Total Page 30 Pages
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