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Cypress Semiconductor Electronic Components Datasheet

CYP15G04K100 Datasheet

(CYPxxx) Programmable Serial Interface

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CYP15G04K100 pdf
.com Programm(HaigbhleSSpeerieadl IDnetevrifcaecse)PRELIMINARY
Sheet4U Programmable BandwidthFeatures
ta• 200 Mbps – 1.5 Gbps, 2.5 Gbps serial signaling rate
a• Flexible parallel-to-serial conversion in transmit path
.D• Flexible serial-to-parallel conversion in receive path
w• Multiple selectable loopback/loop-through modes
w• 100K to 200K usable gates of CPLD logic
w • 240K to 480 Kb of integrated memory
— 192K to 384Kb of synchronous or asynchronous
mSRAM
o— 48K to 96Kb of true Dual-Port or FIFO RAM
• Internal transmit and receive PLLs
.c• Logic dedicated Spread Aware PLL
• Transmit FIFO for flexible variable phase clocking
• Differential CML serial input with internal termination
Uand DC-restoration
t4• Differential CML serial output with source matched im-
pedance of 50
• 160–240 user programmable I/Os
e• Any Volt™ I/O interface
— Programmable as 1.8V, 2.5V, 3.3V
e• Multiple I/O standards
h— LVCMOS, LVTTL, 3.3V PCI, SSTL2(I-II), SSTL3(I-II),
HSTL(I-IV), and GTL+
S• Direct interface to standard fiber-optic modules
• Designed to drive:
ta— Fiberoptic Modules
— Copper Cables
a— Circuit Board Traces
— Backplane Links
.D— Box-to-Box Links
— Chip-to-Chip Communication
w• Extremely flexible clocking options
— Four global clocks
w— Up to 192 additional product term clocks
— Clock polarity at every register
w om• Carry chain logic for fast and efficient arithmetic
.coperations
• Fully PCI compliant (Rev. 2.2)
U• JTAG programming interface with boundary scan sup-
t4port
e• High-Speed (HS) or Frequency Agile (FA) Programma-
eble Serial Interface™ (PSI™) versions available
hHigh-Speed PSI Features
taS• 2.5 Gbps/channel serial signaling rate
a• Full Bellcore and ITU jitter compliance
.DNote:
1. For more detail, refer to the Frequency Agile PSIdata sheet.
• Power-saving mode
• Up to two serial channels available to allow:
— High-Bandwidth
— Redundancy
• Supported standards:
— InfiniBand™
— SONET OC-48
Frequency Agile PSI Features[1]
• 200 Mbps–1.5 Gbps serial signaling rate per channel
• Up to eight serial channels available to allow:
— Frequency Agile
— Redundancy
• Selectable input and output clocking options
• MultiFrame™ receive framer provides alignment to:
— Bit, byte, half-word, word, multi-word
— COMMA or Full K28.5 detect
— Single or Multi-byte framer for byte alignment
— Low-latency option
• Skew alignment support for multiple bytes of offset
• Selectable parity check/generate
• Serial Built-In-Self-Test (BIST) for at-speed link testing
• Per-channel Link Quality Indicator
— Analog signal detect
— Digital signal detect
— Frequency range detect
• Supported standards:
— Fibre Channel
— Gigabit Ethernet
— ESCON
— DVB
— SMPTE
Development Software
• Warp®
IEEE 1076/1164 VHDL or IEEE 1364 Verilog context
sensitive editing
Active-HDL FSM graphical finite state machine
editor
Active-HDL SIM post-synthesis timing simulator
Architecture Explorer for detailed design analysis
Static Timing Analyzer for critical path analysis
Available on Windows® 95, 98 & NT for $99
Supports all Cypress programmable logic products
wwCypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
wDocument #: 38-02021 Rev. *B
Revised August 31, 2001


Cypress Semiconductor Electronic Components Datasheet

CYP15G04K100 Datasheet

(CYPxxx) Programmable Serial Interface

No Preview Available !

CYP15G04K100 pdf
Programmable Serial Interface
PRELIMINARY (High Speed Devices)
PSI Quick Reference Selection Guide
Logic Gate Density
100K
200K
High-Speed/SONET/SDH
PSI Serial Bandwidth
1 x 2.5 Gbps
2 x 2.5 Gbps
25G01K100
25G02K100
25G02K200
Frequency-Agile
PSI Serial Bandwidth
4 x 0.2 1.5 Gbps
8 x 0.2 1.5 Gbps
15G04K100
15G04K200
15G08K200
PSI Family Standards Supported
PSI Device
SONET/SDH CYS25G01K100
CYS25G02K100
CYS25G02K200
High
Speed
CYP25G01K100
CYP25G02K100
CYP25G02K200
Frequency CYP15G04K100
Agile
CYP15G04K200
CYP15G08K200
SONET/SDH
(OC48/STM16)
X
X
X
InfiniBand
X
X
X
Fibre Gigabit
Channel Ethernet
XX
XX
XX
ESCON
X
X
X
SMPTE
259/292
X
X
X
Custom
X
X
X
X
X
X
X
X
X
PSI Family General Selection Guide
Device
Typical
Gates
Cluster Channel Maximum User
memory memory Programmable
Macrocells (Kbits) (Kbits)
I/O
Package Offering
25G01K100 46K144K
1536
192 48
240 456-BGA (35x35 mm, 1.27 mm pitch)
25G02K100 46K144K
1536
192 48
194 456-BGA (35x35 mm, 1.27 mm pitch)
25G02K200 92K288K
3072
384 96
320 700-BGA (45x45 mm, 1.27 mm pitch)
15G04K100 46K144K
1536
192 48
206 456-BGA (35x35mm, 1.27 mm pitch)
15G04K200 92K288K
3072
384 96
332 700-BGA (45x45 mm, 1.27 mm pitch)
15G08K200 92K288K
3072
384 96
206 700 BGA (45x45 mm, 1.27 mm pitch)
Shaded areas contain advance information.
PSI Family Performance Selection Guide
Device
Channels
&
Link Speed
Total
Bandwidth
fMAX2
(MHz)
25G01K100
1 x 2.5 Gbps
2.5 Gbps
222
25G02K100
2 x 2.5 Gbps
5.0 Gbps
222
25G02K200
2 x 2.5 Gbps
5.0 Gbps
181
15G04K100
4 x 0.2 1.5 Gbps
6.0 Gbps
222
15G04K200
4 x 0.2 1.5 Gbps
6.0 Gbps
181
15G08K200
8 x 0.2 1.5 Gbps
12.0 Gbps
181
Note:
2. Standby ICC values are with logic PLL not utilized, no output load, and stable inputs.
3. Shaded area is preliminary
Logic Speed
tPD Pin-to-Pin (ns)
7.5
7.5
8.5
7.5
8.5
8.5
Standby
ICC[2]
16 mA
22 mA
22 mA
18 mA
18 mA
26 mA
Document #: 38-02021 Rev. *B
Page 2 of 58


Part Number CYP15G04K100
Description (CYPxxx) Programmable Serial Interface
Maker Cypress Semiconductor
Total Page 30 Pages
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