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Cypress Semiconductor Electronic Components Datasheet

GVT71512B18 Datasheet

(GVT7xxxx) 256K x 36 / 512K x 18 Sunchronous Burse Flowthrough SRAM

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GVT71512B18 pdf
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1CY7C1361A
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
256K x 36/512K x 18 Synchronous Burst Flowthrough SRAM
Features
• Fast access times: 6.0, 6.5, 7.0, and 8.0 ns
• Fast clock speed: 150, 133, 117, and 100 MHz
• 1 ns set-up time and hold time
• Fast OE access times: 3.5 ns and 4.0 ns
• 3.3V –5% and +10% power supply
• 3.3V or 2.5V I/O supply
• 5V tolerant inputs except I/Os
• Clamp diodes to VSS at all inputs and outputs
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Multiple chip enables for depth expansion:
three chip enables for TA(GVTI)/A(CY) package version
and two chip enables for B(GVTI)/BG(CY) and
T(GVTI)/AJ(CY) package versions
• Address pipeline capability
• Address, data and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
• JTAG boundary scan for B and T package version
• Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid
Array) and 100-pin TQFP packages
Functional Description
The Cypress Synchronous Burst SRAM family employs high-
speed, low-power CMOS designs using advanced triple-layer
polysilicon, double-layer metal technology. Each memory cell
consists of four transistors and two high-valued resistors.
The GVT71256B36/CY7C1361A and GVT71512B18/
CY7C1363A SRAMs integrate 262,144x36 and 524,288x18
SRAM cells with advanced synchronous peripheral circuitry
and a 2-bit counter for internal burst operation. All synchro-
nous inputs are gated by registers controlled by a positive-
edge-triggered Clock Input (CLK). The synchronous inputs in-
clude all addresses, all data inputs, address-pipelining Chip
Enable (CE), depth-expansion Chip Enables (CE2 and CE2),
Burst Control Inputs (ADSC, ADSP, and ADV), Write Enables
(BWa, BWb, BWc, BWd, and BWE), and Global Write (GW).
However, the CE2 chip enable input is only available for TA(GV-
TI)/A(CY) package version.
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). The data outputs (Q), enabled by
OE, are also asynchronous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa. BWb controls DQb. BWc controls DQc. BWd
controls DQd. BWa, BWb, BWc, and BWd can be active only
with BWE being LOW. GW being LOW causes all bytes to be
written. The x18 version only has 18 data inputs/outputs (DQa
and DQb) along with BWa and BWb (no BWc, BWd, DQc, and
DQd).
For the B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package ver-
sions, four pins are used to implement JTAG test capabilities:
Test Mode Select (TMS), Test Data-In (TDI), Test Clock (TCK),
and Test Data-Out (TDO). The JTAG circuitry is used to serially
shift data to and from the device. JTAG inputs use
LVTTL/LVCMOS levels to shift data during this testing mode of
operation. The TA package version does not offer the JTAG
capability.
The GVT71256B36 and GVT71512B18 operate from a +3.3V
power supply. All inputs and outputs are LVTTL compatible.
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
7C1361A-150
7C1363A-150
71256B36-6
71512B18-6
6.0
400
10
7C1361A-133
7C1363A-133
71256B36-6.5
71512B18-6.5
6.5
360
10
7C1361A-117
7C1363A-117
71256B36-7
71512B18-7
7.0
320
10
7C1361A-100
7C1363A-100
71256B36-8
71512B18-8
8.0
270
10
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June 11, 2001


Cypress Semiconductor Electronic Components Datasheet

GVT71512B18 Datasheet

(GVT7xxxx) 256K x 36 / 512K x 18 Sunchronous Burse Flowthrough SRAM

No Preview Available !

GVT71512B18 pdf
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
256K x 36 (CY7C1361A/GVT71256B36) Functional Block Diagram[1]
BWa#
BWE#
BYTE a WRITE
DQ
CLK
BWb#
BYTE b WRITE
DQ
GW#
BWc#
BYTE c WRITE
DQ
BWd#
BYTE d WRITE
DQ
CE#
CE2
[2]CE2#
ENABLE
DQ
OE#
ZZ
ADSP#
A
ADSC#
Power Down Logic
16
Address
Register
Input
Register
ADV#
A1-A0
MODE
CLR
Binary
Counter
& Logic
512K x 18 (CY7C1363A/GVT71512B18)Functional Block Diagram
BWb#
BWE#
BYTE b
WRITE
DQ
DQa,DQb
DQc,DQd
BWa#
GW#
BYTE a
WRITE
DQ
CE#
CE2
[2]CE2#
ZZ
OE#
ADSP#
Power Down Logic
ENABLE
DQ
Input
Register
A
ADSC#
17
Address
Register
CLR
DQa,D
Qb
ADV#
A1-A0
MODE
Binary
Counter
& Logic
Notes:
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information.
2. CE2 is for AJ/TA version only.
2


Part Number GVT71512B18
Description (GVT7xxxx) 256K x 36 / 512K x 18 Sunchronous Burse Flowthrough SRAM
Maker Cypress Semiconductor
Total Page 28 Pages
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