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CY28447 Datasheet Preview

CY28447 Datasheet

Clock Generator

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CY28447 pdf
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PRELIMINARY
CY28447
Clock Generator for Intel® Calistoga Chipset
Features
• Compliant to Intel® CK410M
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz differential SRC clocks
• 96 MHz differential dot clock
• 27 MHz Spread and Non-spread video clock
• 48 MHz USB clock
• SRC clocks independently stoppable through
CLKREQ#[1:9]
• 96/100 MHz spreadable differential video clock
Block Diagram
• 33 MHz PCI clocks
• Buffered Reference Clock 14.318MHz
• Low-voltage frequency select inputs
• I2C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 72-pin QFN package
CPU
x2 / x3
SRC
x9/11
PCI REF DOT96 USB_48M
x5 x 2 x 1
x1
LCD
x1
27M
x2
Pin Configuration
XIN
XOUT
SEL_CLKREQ
PCI_STP#
CPU_STP#
CLKREQ[1:9]#
ITP_SEL
FS[C:A]
14.318MHz
Crystal
PLL Reference
CPU
PLL Divider
FCTSEL1
VTT_PWRGD#/PD
SDATA
SCLK
LVDS
PLL
Divider
Fixed
PLL
Divider
27M
PLL
I2C
Logic
Divider
VDD
REF[1:0]
IREF
VDD
CPUT[0:1]
CPUC[0:1]
VDD
CPUT2_ITP/SRCT10
CPUC2_ITP/SRCC10
VDD
SRCT(1:9])
SRCC(1:9])
VDD
PCI[1:4]
VDD_PCI
PCIF0
VDD
SRCT0/100MT_SST
SRCC0/100MC_SST
VDD48
27MSpread
VDD48
DOT96T
DOT96C
VDD48
48M
VDD48
27MNon-spread
VDD_SRC
SRCC_9
SRCT_9
VSS_SRC
CPUC2_ITP / SRCC_10
CPUT2_ITP / SRCT_10
VDDA
VSSA
IREF
CPUC1
CPUT1
VDD_CPU
CPUC0
CPUT0
VSS_CPU
SCLK
SDATA
VDD_REF
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
1 54
2 53
3 52
4 51
5 50
6 49
7 48
8 47
9
CY28447
46
10 45
11 44
12 43
13 42
14 41
15 40
16 39
17 38
18 37
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
VDD_SRC
SRCC_2
SRCT_2
SRCC_1
SRCT_1
VDD_SRC
SRCC_0 / LCD100MC
SRCT_0 / LCD100MT
CLKREQ1#
FSB/TEST_MODE
DOT96C / 27M_SS
DOT96T / 27M_NSS
VSS_48
48M / FSA
VDD_48
VTT_PWRGD# / PD
CLKREQ7#
PCIF0/ITP_SEL
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555 Fax:(408) 855-0550
Page 1 of 21
www.SpectraLinear.com



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CY28447 Datasheet Preview

CY28447 Datasheet

Clock Generator

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CY28447 pdf
CY28447
Pin Description
Pin No.
Name
Type
Description
1, 49, 54, 65 VDD_SRC
PWR 3.3V power supply for outputs.
2, 3, 50, 51,
52, 53, 55,
56, 58, 59,
60, 61, 63,
64, 66, 67,
69, 70
SRCT/C[1:9]
O, DIF 100 MHz Differential serial reference clocks.
4, 68
VSS_SRC
GND Ground for outputs.
5, 6 CPUT2_ITP/SRCT10, O, DIF Selectable differential CPU or SRC clock output.
CPUC2_ITP/SRCC10
ITP_SEL = 0 @ VTT_PWRGD# assertion = SRC10
ITP_SEL = 1 @ VTT_PWRGD# assertion = CPU2
7 VDDA
PWR 3.3V power supply for PLL.
8 VSSA
GND Ground for PLL.
9 IREF
I A precision resistor is attached to this pin which is connected to the internal
current reference.
10, 11, 13, 14 CPUT/C[0:1]
O, DIF Differential CPU clock outputs.
12 VDD_CPU
PWR 3.3V power supply for outputs.
15 VSS_CPU
GND Ground for outputs.
16 SCLK
I SMBus-compatible SCLOCK.
17 SDATA
I/O, OD SMBus-compatible SDATA.
18 VDD_REF
PWR 3.3V power supply for outputs.
19 XOUT
O, SE 14.318 MHz crystal output.
20 XIN
I 14.318 MHz crystal input.
21 VSS_REF
GND Ground for outputs.
22 REF1
O Fixed 14.318 MHz clock output.
23 REF0/FSC_TESTSEL I/O,PD Fixed 14.318 clock output / 3.3V-tolerant input for CPU frequency
selection/Selects test mode if pulled to VIMFS_C when VTT_PWRGD# is
asserted LOW.
Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifi-
cations.
24 CPU_STP#
I, PU 3.3V LVTTL input for CPU_STP# active LOW.
25 PCI_STP#
I, PU 3.3V LVTTL input for PCI_STP# active LOW.
26, 28, 29,
38, 46, 57,
62, 71, 72
CLKREQ[1:9]#
I, PU 3.3V LVTTL input for enabling assigned SRC clock (active LOW).
27, 32, 33 PCI[1:3]
O, SE 33 MHz clock outputs
30, 36
VDD_PCI
PWR 3.3V power supply for outputs.
31, 35
VSS_PCI
GND Ground for outputs.
34
PCI4/FCTSEL1
I/O, PD 33 MHz clock output / 3.3V LVTTL input for selecting pins 47,48 (SRC[T/C]0,
100M[T/C]) and pins 43,44 (DOT96[T/C] and 27M Spread and Non-spread)
(sampled on the VTT_PWRGD# assertion).
FCTS E L1 P in 43
0 DOT96T
1 27M_NSS
Pin 44
DOT96C
2 7 M_ S S
Pin 47 Pin 48
96/100M_T 96/100M_C
SRCT0 SRCC0
37
ITP_SEL/PCIF0
I/O,PD, 3.3V LVTTL input to enable SRC10 or CPU2_ITP / 33-MHz clock output.
SE (sampled on the VTT_PWRGD# assertion).
1 = CPU2_ITP, 0 = SRC10
Rev 1.0, November 20, 2006
Page 2 of 21


Part Number CY28447
Description Clock Generator
Maker ETC
Total Page 21 Pages
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