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VSC7123QU Datasheet Preview

VSC7123QU Datasheet

10-Bit Transceiver for Fibre Channel and Gigabit Ethernet

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VSC7123QU pdf
VELOCITYTM
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
Features
• 802.3z Gigabit Ethernet-Compliant
1.25 Gb/s Transceiver
• ANSI X3T11 Fibre Channel-Compliant
1.0625 Gb/s Transceiver
• 0.98 to 1.36 Gb/s Full-Duplex Operation
• 10-Bit TTL Interface for Transmit and
Receive Data
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
• Automatic Lock-to-Reference
• RX Cable Equalization
• Analog/Digital Signal Detection
• JTAG Access Port for Testability
• Single +3.3V Supply, 650mW Typical
• Packages: 64-Pin 10mm and 14mm PQFP and
10mm TQFP
General Description
The VSC7123 is a full-speed Fibre Channel and Gigabit Ethernet Transceiver with industry-standard
pinouts. The VSC7123 accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of REFCLK
and serializes the data onto the TX PECL differential outputs at a baud rate which is 10 times the REFCLK
frequency. Serial data input on the RX PECL differential inputs is resampled by the Clock Recovery Unit
(CRU) and deserialized onto the 10-bit receive data bus synchronously to complementary divide-by-twenty
clocks. The VSC7123 receiver detects “Comma” characters for frame alignment. An analog/digital signal
detection circuit indicates that a valid signal is present on the RX input. A cable equalizer compensates for
InterSymbol Interference (ISI) in order to increase maximum cable distances. The VSC7123 is a higher
performance, lower cost replacement for the VSC7125 and VSC7135.
VSC7123 Block Diagram
R(0:9)
10
RCLK
RCLKN
COMDET
ENCDET
EWRAP
SIGDET
T(0:9)
10
REFCLK
QD
Serial to
Q Parallel D
QD
Comma
Detect
÷10 Clock
÷20 Recovery
2:1
Signal
Detect
RX+
RX-
DQ
x10 Clock
Multiply
Parallel
to Serial
DQ
TX+
TX-
NOT SHOWN: JTAG Boundary Scan
G52212-0, Rev 4.3
03/25//01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 1



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VSC7123QU Datasheet Preview

VSC7123QU Datasheet

10-Bit Transceiver for Fibre Channel and Gigabit Ethernet

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VSC7123QU pdf
VELOCITYTM
VITESSE
SEMICONDUCTOR CORPORATION
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Data Sheet
VSC7123
Functional Description
Clock Synthesizer
The VSC7123 clock synthesizer multiplies the reference frequency provided on the REFCLK pin by 10 to
achieve a baud rate clock between 0.98GHz and 1.36GHz. The on-chip Phase Lock Loop (PLL) uses a single
external 0.1µF capacitor to control the Loop Filter.
Serializer
The VSC7123 accepts TTL input data as a parallel 10-bit character on the T(0:9) bus, which is latched into
the input register on the rising edge of REFCLK. This data is serialized and transmitted on the TX PECL
differential outputs at a baud rate that is 10 times the frequency of the REFCLK, with bit T0 transmitted first.
User data should be encoded using 8B/10B block code or equivalent.
Transmission Character Interface
An encoded byte is 10 bits and is referred to as a transmission character. The 10 bit interface on the
VSC7123 corresponds to a transmission character. This mapping is illustrated in Figure 1.
Figure 1: Transmission Order and Mapping of an 8B/10B Character
Parallel Data Bits
8B/10B Bit Position
Comma Character
T9 T8 T7 T6 T5 T4 T3 T2 T1 T0
jhgf i e dc ba
XXX1 1 1 1 1 0 0
Last Data Bit Transmitted
First Data Bit Transmitted
Clock Recovery
The VSC7123 accepts differential high-speed serial inputs on the RX+/RX- pins, extracts the clock and
retimes the data. Equalizers are included in the receiver to open the data eye and compensate for InterSymbol
Interference which may be present in the incoming data. The serial bit stream should be encoded to provide DC
balance and limited run length by an 8B/10B encoding scheme. The Clock Recovery Unit is completely
monolithic and requires no external components. For proper operation, the baud rate of the data stream to be
recovered should be within +200 ppm of 10 times the REFCLK frequency. For example, Gigabit Ethernet
systems would use 125MHz oscillators with a +100ppm accuracy resulting in +200 ppm between VSC7123
pairs.
Deserializer
The recovered serial bit stream is converted into a 10-bit parallel output character. The VSC7123 provides
complementary TTL recovered clocks, RCLK and RCLKN, which are 1/20th of the serial baud rate. The clocks
are generated by dividing down the high-speed recovered clock, which is phase-locked to the serial data. The
Page 2
© VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52212-0, Rev 4.3
03/25/01


Part Number VSC7123QU
Description 10-Bit Transceiver for Fibre Channel and Gigabit Ethernet
Maker ETC
Total Page 18 Pages
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