http://www.datasheet4u.com

900,000+ Datasheet PDF Search and Download

Datasheet4U offers most rated semiconductors datasheets pdf





ETC
ETC

VSC7125QU Datasheet Preview

VSC7125QU Datasheet

1.0625 Gbits/sec Fibre Channel Transceiver

No Preview Available !

VSC7125QU pdf
Data Sheet
VSC7125
VITESSE
SEMICONDUCTOR CORPORATION
1.0625 Gbits/sec Fibre
Channel Transceiver
Features
• ANSI X3T11 Fibre Channel Compatible
1.0625 Gbps Full-duplex Transceiver
• 10 Bit TTL Interface for Transmit and
Receive Data
• Monolithic Clock Synthesis and Clock
Recovery - No External Components
• 106.25 MHz TTL Reference Clock
• Low Power Operation - 650 mW
• Suitable for Both Coaxial and Optical
Link Applications
• 64 Pin, 10mm or 14mm PQFP
• Single +3.3V Power Supply
General Description
The VSC7125 is a full-speed Fibre Channel Transceiver optimized for Disk Drive and other space con-
strained applications. It accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of REFCLK
and serializes it onto the TX PECL differential outputs at a baud rate which is ten times the REFCLK frequency.
The VSC7125 also samples serial receive data on the RX PECL differential inputs, recovers the clock and data,
deserializes it onto the 10-bit receive data bus, outputs two recovered clocks at one twentieth of the incoming
baud rate and detects Fibre Channel “Comma” characters. The VSC7125 contains on-chip PLL circuitry for
synthesis of the baud-rate transmit clock, and extraction of the clock from the received serial stream. These cir-
cuits are fully monolithic and require no external components.
VSC7125 Block Diagram
EWRAP
R0:9
RCLK
RCLKN
COM_DET
EN_CDET
T0:9
10
QD
Serial to
Parallel
÷ 10
÷ 20
Resync Frame
Logic
Comma
Detect
Retimed
Data
QD
Recovered
Clock
Clock
Recovery
2:1
10
DQ
Parallel
to Serial
Serial Data
Synthesized
Clock
DQ
RX+
RX-
TX+
TX-
REFCLK
PLL Clock
Multiply
G52121-0, Rev. 4.1
4/23/98
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 1



ETC
ETC

VSC7125QU Datasheet Preview

VSC7125QU Datasheet

1.0625 Gbits/sec Fibre Channel Transceiver

No Preview Available !

VSC7125QU pdf
1.0625 Gbits/sec Fibre
Channel Transceiver
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7125
Functional Description
Clock Synthesizer
The VSC7125 clock synthesizer multiplies the reference frequency provided on the REFCLK pin by 10 to
achieve a baud rate clock at nominally 1.0625 GHz. The clock synthesizer contains a fully monolithic PLL
which does not require any external components.
Serializer
The VSC7125 accepts TTL input data as a parallel 10 bit character on the T0:9 bus which is latched into the
input latch on the rising edge of REFCLK. This data will be serialized and transmitted on the TX PECL differ-
ential outputs at a baud rate of ten times the frequency of the REFCLK input, with bit T0 transmitted first. User
data should be encoded for transmission using the 8B/10B block code described in the Fibre Channel specifica-
tion, or an equivalent, edge rich, DC-balanced code.
Transmission Character Interface
In Fibre Channel, an encoded byte is 10 bits and is referred to as a transmission character. The 10 bit inter-
face on the VSC7125 corresponds to a transmission character. This mapping is illustrated below.
Figure 1: Transmission Order and Mapping to Fibre Channel Character
Parallel Data Bits
8B/10B Bit Position
Comma Character
T9 T8 T7 T6 T5 T4 T3 T2 T1 T0
j hgf i edcba
XXX1 1 1 1 1 0 0
Last Data Bit Transmitted
First Data Bit Transmitted
Clock Recovery
The VSC7125 accepts differential high speed serial inputs on the RX+/RX- pins, extracts the clock and
retimes the data. The serial bit stream should be encoded to provide DC balance and limited run length by a
Fibre Channel compatible 8B/10B transmitter or equivalent. The VSC7125 clock recovery circuitry is com-
pletely monolithic and requires no external components. For proper operation, the baud rate of the data stream
to be recovered should be within 0.01% of ten times the REFCLK frequency. For example if the REFCLK used
is 106.25MHz, then the incoming serial baud rate must be 1.0625 gigabaud +0.01%.
Deserializer
The retimed serial bit stream is converted into a 10-bit parallel output character. The VSC7125 provides
complementary TTL recovered clocks, RCLK and RCLKN, which are at one twentieth of the serial baud rate.
This architecture is designed to simplify demultiplexing of the 10-bit data characters into a 20-bit halfword in
the downstream controller chip. The clocks are generated by dividing down the high-speed clock which is phase
locked to the serial data. The serial data is retimed by the internal high-speed clock, and deserialized. The
Page 2
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52121-0, Rev. 4.1
4/23/98


Part Number VSC7125QU
Description 1.0625 Gbits/sec Fibre Channel Transceiver
Maker ETC
Total Page 16 Pages
PDF Download
VSC7125QU pdf
Download PDF File
VSC7125QU pdf
View for Mobile



Buy Electronic Components




Related Datasheet

1 VSC7125QN 1.0625 Gbits/sec Fibre Channel Transceiver ETC
ETC
VSC7125QN pdf
2 VSC7125QU 1.0625 Gbits/sec Fibre Channel Transceiver ETC
ETC
VSC7125QU pdf






Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

site map

webmaste! click here

contact us

Buy Components