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Holt Integrated Circuits
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HI-8588 Datasheet Preview

HI-8588 Datasheet

ARINC 429 LINE RECEIVER

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HI-8588 pdf
January 2001
HI-8588
DESCRIPTION
The HI-8588 is an ARINC 429 bus interface receiver and is
available in a SO 8 pin package. The technology is
analog/digital CMOS. The circuitry requires only a 5 volt
supply.
The ARINC bus can be connected directly to the chip. The
typical 10 volt differential signal is translated and input to a
window comparator and latch. The comparator levels are
just below the standard 6.5 volt minimum ARINC data
threshold and just above the standard 2.5 volt maximum
ARINC null threshold.
The TESTA and TESTB inputs bypass the analog for
testing purposes. Also if TESTA and TESTB are both
taken high, the analog powers down and the digital outputs
tri-state allowing wire-or possibilities.
Please refer to the HI-8588-10 for applications where an
external resistance in series with the ARINC inputs is
required for lightning protection or when the digital outputs
need to be a logic zero rather than open circuit when
TESTA and TESTB are both high.
PIN CONFIGURATION
VCC 1
TESTA 2
RINB 3
RINA 4
8 TESTB
7 ROUTB
6 ROUTA
5 GND
SUPPLY VOLTAGES
vcc = 5.0V ± 5%
FUNCTION TABLE
FEATURES
! Direct ARINC 429 line receiver interface
in a small outline package
! Receiver input hystersis at least 2 volts
! Test inputs that bypass analog input and
can power down and tri-state outputs
! Plastic and ceramic package options -
surface mount and DIP
! Mil processing available
PIN DESCRIPTION TABLE
PIN SYMBOL
VCC
TESTA
RINB
RINA
GND
ROUTA
ROUTB
TESTB
FUNCTION
SUPPLY
LOGIC INPUT
ARINC INPUT
ARINC INPUT
POWER
LOGIC OUTPUT
LOGIC OUTPUT
LOGIC INPUT
DESCRIPTION
5 VOLT SUPPLY
CMOS
RECEIVER B INPUT
RECEIVER A INPUT
GROUND
RECEIVER CMOS OUTPUT A
RECEIVER CMOS OUTPUT B
CMOS
(DS8588 Rev. A)
HOLT INTEGRATED CIRCUITS
1
01/01



Holt Integrated Circuits
Holt Integrated Circuits

HI-8588 Datasheet Preview

HI-8588 Datasheet

ARINC 429 LINE RECEIVER

No Preview Available !

HI-8588 pdf
HI-8588
FUNCTIONAL DESCRIPTION
RECEIVER
Figure 1 shows the general architecture of the ARINC 429
receiver. The receiver operates off the VCC supply only.
The inputs RINA and RINB each have series resistors, typi-
cally 35K ohms. They connect to level translators whose
resistance to Ground is typically 10K ohms. Therefore, any
series resistance added to the inputs will affect the voltage
translation.
After level translation, the inputs are buffered and become
inputs to a differential amplifier. The amplitude of the dif-
ferential signal is compared to levels derived from a di-
vider between VCC and Ground. The nominal settings cor-
respond to a One/Zero amplitude of 6.0V and a Null ampli-
tude of 3.3V.
The status of the ARINC receiver input is latched. A Null
input resets the latches and a One or Zero input sets the
latches.
The logic at the output is controlled by the test signal
which is generated by the logical OR of theTestA and
TestB pins. If TestA and TestB are both One, then the re-
ceiver is powered down and the output pins float. The
powerdown does not disconnect the internal resistors at
the ARINC input.
RINA
RINB
ESD
PROTECTION
AND
TRANSLATION
ONE
NULL
ZERO
NULL
SQ
LATCH
R
SQ
LATCH
R
TEST
TEST
TESTA
TEST
TEST
TESTB
FIGURE 1 - RECEIVER BLOCK DIAGRAM
ROUTA
TESTA ' TESTB
ROUTB
TESTA ' TESTB
APPLICATION INFORMATION
Figure 2 shows a possible application of the
HI-8588 interfacing an ARINC receive channel
to the HI-6010 which in turn interfaces to an
8-bit bus.
2
8
4
3
5
1
6
7
1
6
7
8
2
3
45
FIGURE 2 - APPLICATION DIAGRAM
HOLT INTEGRATED CIRCUITS
2


Part Number HI-8588
Description ARINC 429 LINE RECEIVER
Maker Holt Integrated Circuits
Total Page 6 Pages
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