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IC62LV12816DL Datasheet Preview

IC62LV12816DL Datasheet

128 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM

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IC62LV12816DL
IC62LV12816DLL
Document Title
128 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM
Revision History
Revision No
0A
History
Initial Draft
Draft Date
June 7,2002
Remark
Preliminary
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
LPSR025-0A 6/7/2002
1



ICSI
ICSI

IC62LV12816DL Datasheet Preview

IC62LV12816DL Datasheet

128 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM

No Preview Available !

IC62LV12816DL pdf
IC62LV12816DL
IC62LV12816DLL
128K x 16 LOW VOLTAGE, ULTRA
LOW POWER CMOS STATIC RAM
Preliminary
FEATURES
• High-speed access times: 55, 70, 100 ns
CMOS low power operation
--60mW (typical)* operating
--3µW (typical)* CMOS standby
• TTL compatible interface levels
• Single 2.7V-3.6V Vcc power supply
• Fully static operation: no clock or refresh re-
quired
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Available in the 44-pin TSOP-2 and 48-pin
6x8mm TF-BGA
• CE2 pin only for 48-pin TF-BGA.
* Typical values are measured at VCC=3.0V, TA=25°C
DESCRIPTION
The ICSI IC62LV12816DL and IC62LV12816DLL are low-
power,2,097,152 bit static RAMs organized as 131,072 words
by 16 bits. They are fabricated using ICSI's high-performance
CMOS technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-performance
and low power consumption devices.
When CE1 is HIGH or when CE2 is low (deselected) or both LB
and UB are HIGH, the device assumes a standby mode at
which the power dissipation can be reduced by using CMOS
input levels.
Easy memory expansion is provided by using Chip Enable
Output and Enable inputs, CE1, CE2 and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower Byte
(LB) access.
The IC62LV12816DL and IC62LV12816DLL are packaged in
the JEDEC standare 44-pin TSOP-2 and 48-pin 6*8mm TF-
BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K x 16
MEMORY ARRAY
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
CE1, CE2
OE
WE
UB
LB
CONTROL
CIRCUIT
COLUMN I/O
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2 Integrated Circuit Solution Inc.
LPSR025-0A 6/7/2002


Part Number IC62LV12816DL
Description 128 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM
Maker ICSI
Total Page 12 Pages
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1 IC62LV12816DL 128 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM ICSI
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2 IC62LV12816DLL 128 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM ICSI
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IC62LV12816DLL pdf






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