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Integrated Silicon Solution Electronic Components Datasheet

IS42S81600B Datasheet

8Meg x16 128-MBIT SYNCHRONOUS DRAM

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IS42S81600B pdf
IS42S81600B
IS42S16800B
16Meg x 8, 8Meg x16
128-MBIT SYNCHRONOUS DRAM
ISSI®
MAY 2006
FEATURES
• Clock frequency: 167, 143, 133 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Power supply
IS42S81600B
VDD VDDQ
3.3V 3.3V
IS42S16800B
3.3V 3.3V
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
www.DataSheet4U.com Sequential/Interleave
• Auto Refresh (CBR)
• Self Refresh with programmable refresh periods
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
• Industrial Temperature Availability
• Lead-free Availability
OVERVIEW
ISSI's 128Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock
input.The 128Mb SDRAM is organized as follows.
IS42S81600B
4M x8x4 Banks
54-pin TSOPII
IS42S16800B
2M x16x4 Banks
54-pin TSOPII
KEY TIMING PARAMETERS
Parameter
-6 -7 -75E
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
67
10 7.5
Clk Frequency
CAS Latency = 3
CAS Latency = 2
167 143
100 133
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
5.4
5.4
6
6
Unit
ns
ns
Mhz
Mhz
ns
ns
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. E
05/01/06
1


Integrated Silicon Solution Electronic Components Datasheet

IS42S81600B Datasheet

8Meg x16 128-MBIT SYNCHRONOUS DRAM

No Preview Available !

IS42S81600B pdf
IS42S81600B, IS42S16800B
ISSI ®
DEVICE OVERVIEW
The 128Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V VDD
and 3.3V VDDQ memory systems containing 134,217,728
bits. Internally configured as a quad-bank DRAM with a
synchronous interface. Each 33,554,432-bit bank is orga-
nized as 4,096 rows by 512 columns by 16 bits or 4,096 rows
by 1,024 columns by 8 bits.
The 128Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK. All
inputs and outputs are LVTTL compatible.
The 128Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE func-
tion enabled. Precharge one bank while accessing one of the
other three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting at
a selected location and continuing for a programmed num-
ber of locations in a programmed sequence. The registra-
tion of an ACTIVE command begins accesses, followed by
a READ or WRITE command. The ACTIVE command in
conjunction with address bits registered are used to select
the bank and row to be accessed (BA0, BA1 select the
bank; A0-A11 select the row). The READ or WRITE
commands in conjunction with address bits registered are
used to select the starting column location for the burst
access.
Programmable READ or WRITE burst lengths consist of 1,
2, 4 and 8 locations or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM (FOR 2MX16X4 BANKS ONLY)
www.DataSheet4U.com
CLK
CKE
CS
RAS
CAS
WE
A10
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
COMMAND
DECODER
&
CLOCK
GENERATOR
MODE
REGISTER
12
ROW
ADDRESS
12 LATCH
REFRESH
CONTROLLER
SELF
REFRESH
CONTROLLER
REFRESH
COUNTER
ROW
ADDRESS
BUFFER
12
12
DATA IN
BUFFER
16 16
2
DQML
DQMH
DQ 0-15
DATA OUT
BUFFER
16 16
VDD/VDDQ
Vss/VssQ
4096
4096
4096
4096
MEMORY CELL
ARRAY
BANK 0
SENSE AMP I/O GATE
COLUMN
ADDRESS LATCH
9
BURST COUNTER
COLUMN
ADDRESS BUFFER
BANK CONTROL LOGIC
512
(x 16)
COLUMN DECODER
9
2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. E
05/01/06


Part Number IS42S81600B
Description 8Meg x16 128-MBIT SYNCHRONOUS DRAM
Maker ISSI
Total Page 30 Pages
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