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Integrated Silicon Solution Electronic Components Datasheet

IS42SM16800E Datasheet

128Mb Mobile Synchronous DRAM

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IS42SM16800E pdf
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
16Mx8, 8Mx16, 4Mx32
128Mb Mobile Synchronous DRAM
FEATURES
• Fully synchronous; all signals referenced to a positive
clock edge
• Internal bank for hiding row access and precharge
• Programmable CAS latency: 2, 3
• Programmable Burst Length: 1, 2, 4, 8, and Full Page
• Programmable Burst Sequence:
• Sequential and Interleave
• Auto Refresh (CBR)
• TCSR (Temperature Compensated Self Refresh)
• PASR (Partial Arrays Self Refresh): 1/16, 1/8, 1/4, 1/2,
and Full
• Deep Power Down Mode (DPD)
• Driver Strength Control (DS): 1/4, 1/2, and Full
OPTIONS
• Configurations:
- 16M x 8
- 8M x 16
- 4M x 32
• Power Supply
IS42SMxxx – Vdd/Vddq = 3.3 V
IS42RMxxx – Vdd/Vddq = 2.5 V
• Packages:
x8 / x16 –TSOP II (54), BGA (54) [x16 only]
x32 – TSOP II (86), BGA (90)
• Temperature Range:
Commercial (0°C to +70°C)
Industrial (–40 ºC to 85 ºC)
APRIL 2011
DESCRIPTION
ISSI's 128Mb Mobile Synchronous DRAM achieves high-
speed data transfer using pipeline architecture. All input
and output signals refer to the rising edge of the clock
input. Both write and read accesses to the SDRAM are
burst oriented. The 128Mb Mobile Synchronous DRAM
is designed to minimize current consumption making it
ideal for low-power applications. Both TSOP and BGA
packages are offered, including industrial grade products.
KEY TIMING PARAMETERS
Parameter
CLK Cycle Time
CAS Latency = 3
CAS Latency = 2
CLK Frequency
CAS Latency = 3
CAS Latency = 2
Access Time from CLK
CAS Latency = 3
CAS Latency = 2
-6
6
10
166
100
5.4
8
-7 -75E Unit
7 ns
10 7.5 ns
143 Mhz
100 133 Mhz
5.4 ns
8 5.4 ns
ADDRESSING TABLE
Parameter
Configuration
Refresh Count
Row Addressing
Column Addressing
Bank Addressing
Precharge Addressing
16M x 8
4M x 8 x 4 banks
4K/64ms
A0-A11
A0-A9
BA0, BA1
A10
8M x 16
2M x 16 x 4 banks
4K/64ms
A0-A11
A0-A8
BA0, BA1
A10
4M x 32
1M x 32 x 4 banks
4K/64ms
A0-A11
A0-A7
BA0, BA1
A10
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. - www.issi.com
Rev.  B
04/15/2011
1
Free Datasheet http://www.datasheet4u.com/


Integrated Silicon Solution Electronic Components Datasheet

IS42SM16800E Datasheet

128Mb Mobile Synchronous DRAM

No Preview Available !

IS42SM16800E pdf
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
General Description
ISSI’s 128Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V – 2.5V
VDD and 3.3V – 2.5V VDDQ memory systems containing 134,271,728 bits. Internally configured as a quad-bank
DRAM with a synchronous interface. The 128Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving,
power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are
LVTTL (VDD = 3.3V) or LVCMOS (VDD = 2.5V) compatible. The 128Mb SDRAM has the ability to synchronously
burst data at a high data rate with automatic column-address generation, the ability to interleave between internal
banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE
function enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles
and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented
starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The
registration of an Active command begins accesses, followed by a Read or Write command. The ACTIVE command
in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1 select the
bank; A0-A11 (x8, x16 and x32) select the row). The READ or WRITE commands in conjunction with address bits
registered are used to select the starting column location for the burst access. Programmable READ or WRITE burst
lengths consist of 1, 2, 4 and 8 locations, or full page, with a burst terminate option.
Functional Block Diagram (8Mx16)
CLK
CKE
CS
RAS
CAS
WE
A10
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
COMMAND
DECODER
&
CLOCK
GENERATOR
MODE
REGISTER
12
ROW
ADDRESS
12 LATCH
COLUMN
ADDRESS LATCH
9
BURST COUNTER
COLUMN
ADDRESS BUFFER
REFRESH
CONTROLLER
SELF
REFRESH
CONTROLLER
REFRESH
COUNTER
ROW
ADDRESS
BUFFER
12
DATA IN
BUFFER
16 16
2
DQML
DQMH
DQ 0-15
DATA OUT
BUFFER
16 16
VDD/VDDQ
Vss/VssQ
4096
4096
4096
MEMORY CELL
12
4096
ARRAY
BANK 0
SENSE AMP I/O GATE
BANK CONTROL LOGIC
512
(x 16)
COLUMN DECODER
9
2 Integrated Silicon Solution, Inc. - www.issi.com
Rev.  B
04/15/2011
Free Datasheet http://www.datasheet4u.com/


Part Number IS42SM16800E
Description 128Mb Mobile Synchronous DRAM
Maker ISSI
Total Page 25 Pages
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