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Integrated Circuit Systems
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ICS525-12 Datasheet Preview

ICS525-12 Datasheet

(ICS525-11/-12) User Configurable Clock

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ICS525-01/02/11/12
User Configurable Clock
Description
The ICS525-01/02/11/12 are the most flexible way to
generate a high-quality, high-accuracy, high-frequency
clock output from an inexpensive crystal or clock input.
The user can configure the device to produce nearly
any output frequency from any input frequency by
grounding or floating the select pins. Neither
microcontroller, software, nor device programmer are
needed to set the frequency. Using Phase-Locked
Loop (PLL) techniques, the device accepts a standard
fundamental mode, inexpensive crystal to produce
output clocks up to 250 MHz. It can also produce a
highly accurate output clock from a given input clock,
keeping them frequency locked together.
For similar capability with a serial interface, use the
ICS307. For simple multipliers to produce common
frequencies, refer to the ICS50x family of parts, which
are smaller and more cost effective.
These products are intended for clock generation. They
have low output jitter (variation in the output period), but
input to output skew and jitter are not defined nor
guaranteed. For applications which require defined
input to output timing, use the ICS527-01.
Features
Packaged as 28-pin SSOP (150 mil body)
Industrial and commercial versions available in Pb
(lead) free package
User determines the output frequency by setting all
internal dividers
Eliminates need for custom oscillators
No software needed
Online calculator determines register settings
Pull-ups on all select inputs
Input crystal frequency of 5 - 27 MHz
Input clock frequency of 2 - 50 MHz
Very low jitter
Duty cycle of 45/55 up to 200 MHz
Operating voltage of 3.0 V or 5.5 V
Ideal for oscillator replacement
Industrial temperature version available
For Zero Delay, refer to the ICS527
Block Diagram
PD
X1/ICLK
Crystal or clock
input X2
Optional crystal capacitors
Crystal
Oscillator
Reference
Divider
7
R6:R0
2 VDD
Phase Comparator,
Charge Pump, and
Loop Filter
VCO
Divider
VCO
9 2 GND
V8:V0
Output
Divider
3
S2:S0
CLK
REF
MDS 525-01/02/11/12 Q
1
Revision 101105
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com



Integrated Circuit Systems
Integrated Circuit Systems

ICS525-12 Datasheet Preview

ICS525-12 Datasheet

(ICS525-11/-12) User Configurable Clock

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ICS525-12 pdf
www.DataSheet4U.com
Pin Assignment
R5
R6
S0
S1
S2
VDD
X1/ICLK
X2
GND
V0
V1
V2
V3
V4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 R4
27 R3
26 R2
25 R1
24 R0
23 VDD
22 REF
21 CLK
20 GND
19 PD
18 V8
17 V7
16 V6
15 V5
ICS525-01/-02/-11/-12
ICS525-01/02/11/12
User Configurable Clock
Pin Descriptions
Pin
Number
1, 2,
24-28
3, 4, 5
6, 23
7
8
9, 20
10 - 18
Pin
Name
R5, R6,
R0-R4
S0, S1, S2
VDD
X1/ICLK
X2
GND
V0 - V8
19 PD
21 CLK
22 REF
Pin
Type
I(PU)
I(PU)
Power
X1
X2
Power
I(PU)
Input
Output
Output
Pin Description
Reference divider word input pins determined by user. Forms a binary number from 0
to 127.
Select pins for output divider determined by user. See table on page 3
Connect to VDD.
Crystal connection. Connect to a parallel resonant fundamental crystal or input clock.
Crystal connection. Connect to a crystal or leave unconnected for clock.
Connect to ground.
VCO divider word input pins determined by user. Forms a binary number from 0 to
511.
Power-down. Active low. Turns off entire chip when low. Clock outputs stop low.
Output clock determined by status of R0-R6, V-V8, S0-S2, and input frequency.
Reference output. Buffered crystal oscillator (or clock ) output.
KEY: I(PU) = Input with internal pull-up resistor; X1, X2 = crystal connections
MDS 525-01/02/11/12 Q
2
Revision 101105
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com


Part Number ICS525-12
Description (ICS525-11/-12) User Configurable Clock
Maker Integrated Circuit Systems
Total Page 9 Pages
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