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Integrated Circuit Systems
Integrated Circuit Systems

ICSSSTV16857 Datasheet Preview

ICSSSTV16857 Datasheet

DDR 14-Bit Registered Buffer

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ICSSSTV16857 pdf
Integrated
Circuit
Systems, Inc.
ICSSSTV16857
DDR 14-Bit Registered Buffer
Recommended Application:
DDR Memory Modules
Product Features:
• Differential clock signal
• Meets SSTL_2 signal data
• Supports SSTL_2 class I & II specifications
• low-voltage operation
VDD = 2.3V to 2.7V
• 48 pin TSSOP package
Truth Table1
Inputs
RESET#
L
H
H
CLK
X or
Floating
CLK#
X or
Floating
H L or H L or H
D
X or
Floating
H
L
X
Q Outputs
Q
L
H
L
Q (2)
0
Pin Configuration
Q1
Q2
GND
VDDQ
Q3
Q4
Q5
GND
VDDQ
Q6
Q7
VDDQ
GND
Q8
Q9
VDDQ
GND
Q10
Q11
Q12
VDDQ
GND
Q13
Q14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
D1
D2
GND
VDD
D3
D4
D5
D6
D7
CLK#
CLK
VDD
GND
VREF
RESET#
D8
D9
D10
D11
D12
VDD
GND
D13
D14
48-Pin TSSOP & TVSOP
6.10 mm. Body, 0.50 mm. pitch = TSSOP
4.40 mm. Body, 0.40 mm. pitch = TSSOP (TVSOP)
Notes:
1. H = High Signal Level
L = Low Signal Level
= Transition LOW-to-HIGH
= Transition HIGH -to LOW
X = Irrelevant
2. Output level before the indicated
steady state input conditions were
established.
Block Diagram
CLK
CLK#
RESET#
38
39
34
D1
VREF
48
35
R
CLK
D1
1 Q1
16857 Rev D 07/09/01
Third party brands and names are the property of their respective owners.
To 13 Other Channels
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.



Integrated Circuit Systems
Integrated Circuit Systems

ICSSSTV16857 Datasheet Preview

ICSSSTV16857 Datasheet

DDR 14-Bit Registered Buffer

No Preview Available !

ICSSSTV16857 pdf
ICSSSTV16857
General Description
The 14-bit ICSSTV16857 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O Levels
except for the RESET# input which is LVCMOS.
Data flow from D to Q is controlled by the differential clock, CLK, CLK# and RESET#. Data is triggered on the
positive edge of CLK. CLK# must be used to maintain noise margins. RESET# must be supported with LVCMOS
levels as VREF may not be stable during power-up. RESET# is asynchronous and is intended for power-up only and
when low assures that all of the registers reset to the Low State, Q outputs are low, and all input receivers, data and
clock are switched off.
Pin Configuration
PIN NUMBER
24, 23, 20, 19, 18,
15, 14, 11, 10, 7, 6,
5, 2, 1
3, 8, 13, 22,
27, 36, 46
4, 9, 12, 16, 21
25, 26, 29, 30, 31,
32, 33, 40, 41, 42,
43, 44, 47, 48
38
39
28, 37, 45
34
35
PIN NAME
Q (14:1)
GND
VDDQ
D (14:1)
CLK
CLK#
VDD
RESET#
VREF
TYPE
OUTPUT
Data output
DESCRIPTION
PWR
PWR
INPUT
INPUT
INPUT
PWR
INPUT
INPUT
Ground
Output supply voltage
Data input
Positive clock input
Negative clock input
Core supply voltage
Reset (active low)
Input reference voltage
Third party brands and names are the property of their respective owners.
2


Part Number ICSSSTV16857
Description DDR 14-Bit Registered Buffer
Maker Integrated Circuit Systems
Total Page 8 Pages
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