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Integrated Device Technology Electronic Components Datasheet

IDT72V3640 Datasheet

3.3 VOLT HIGH-DENSITY SUPERSYNC II 36-BIT FIFO

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IDT72V3640 pdf
3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO
1,024 x 36, 2,048 x 36
IDT72V3640, IDT72V3650
4,096 x 36, 8,192 x 36
IDT72V3660, IDT72V3670
16,384 x 36, 32,768 x 36
IDT72V3680, IDT72V3690
65,536 x36, 131,072 x 36
IDT72V36100, IDT72V36110
FEATURES:
Choose among the following memory organizations:Commercial
IDT72V3640 1,024 x 36
IDT72V3650 2,048 x 36
IDT72V3660 4,096 x 36
IDT72V3670 8,192 x 36
IDT72V3680 16,384 x 36
IDT72V3690 32,768 x 36
IDT72V36100 65,536 x 36
IDT72V36110 131,072 x 36
133 MHz operation (7.5 ns read/write cycle time)
User selectable input and output port bus-sizing
- x36 in to x36 out
- x36 in to x18 out
- x36 in to x9 out
- x18 in to x36 out
- x9 in to x36 out
Big-Endian/Little-Endian user selectable byte representation
5V input tolerant
Fixed, low first word latency
Zero latency retransmit
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
Program programmable flags by either serial or parallel means
Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
Independent Read and Write Clocks (permit reading and writing
simultaneously)
Available in the 128-pin Thin Quad Flat Pack (TQFP)
High-performance submicron CMOS technology
Industrial temperature range (–40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
WEN WCLK
D0 -Dn (x36, x18 or x9)
LD SEN
WRITE CONTROL
LOGIC
BE
IP
BM
IW
OW
MRS
PRS
WRITE POINTER
CONTROL
LOGIC
BUS
CONFIGURATION
RESET
LOGIC
INPUT REGISTER
RAM ARRAY
1,024 x 36, 2,048 x 36
4,096 x 36, 8,192 x 36
16,384 x 36, 32,768 x 36
65,536 x 36, 131,072 x36
OFFSET REGISTER
FLAG
LOGIC
READ POINTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
OUTPUT REGISTER
READ
CONTROL
LOGIC
RT
RM
RCLK
REN
OE Q0 -Qn (x36, x18 or x9)
4667 drw 01
The SuperSync II FIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
© 2001 Integrated Device Technology, Inc.
1
APRIL 2001
DSC-4667/3


Integrated Device Technology Electronic Components Datasheet

IDT72V3640 Datasheet

3.3 VOLT HIGH-DENSITY SUPERSYNC II 36-BIT FIFO

No Preview Available !

IDT72V3640 pdf
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION:
The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690/
72V36100/72V36110 are exceptionally deep, high speed, CMOS First-In-
First-Out (FIFO) memories with clocked read and write controls and a flexible
Bus-Matching x36/x18/x9 data flow. These FIFOs offer several key user
benefits:
• Flexible x36/x18/x9 Bus-Matching on both read and write ports
• The period required by the retransmit operation is fixed and short.
• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan
empty FIFO to the time it can be read, is fixed and short.
• High density offerings up to 4 Mbit
Bus-Matching Sync FIFOs are particularly appropriate for network, video,
telecommunications, data communications and other applications that need to
buffer large amounts of data and match busses of unequal sizes.
Each FIFO has a data input port (Dn) and a data output port (Qn), both of
which can assume either a 36-bit, 18-bit or a 9-bit width as determined by the
state of external control pins Input Width (IW), Output Width (OW), and Bus-
Matching (BM) pin during the Master Reset cycle.
The input port is controlled by a Write Clock (WCLK) input and a Write Enable
(WEN)input. DataiswrittenintotheFIFOoneveryrisingedgeofWCLKwhen
WEN is asserted. The output port is controlled by a Read Clock (RCLK) input
andReadEnable(REN)input. DataisreadfromtheFIFOoneveryrisingedge
PIN CONFIGURATIONS
INDEX
WEN
SEN
DNC(1)
VCC
DNC(1)
IW
D35
D34
D33
D32
VCC
D31
D30
GND
D29
D28
D27
D26
D25
D24
D23
GND
D22
VCC
D21
D20
D19
D18
GND
D17
D16
D15
D14
D13
VCC
D12
GND
D11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102 OE
101 VCC
100 VCC
99 Q35
98 Q34
97 Q33
96 Q32
95 GND
94 GND
93 Q31
92 Q30
91 Q29
90 Q28
89 Q27
88 Q26
87 VCC
86 Q25
85 Q24
84 GND
83 GND
82 Q23
81 Q22
80 Q21
79 Q20
78 Q19
77 Q18
76 GND
75 Q17
74 Q16
73 VCC
72 VCC
71 Q15
70 Q14
69 Q13
68 Q12
67 GND
66 Q11
65 Q10
NOTE:
1. DNC = Do Not Connect.
TQFP (PK128-1, order code: PF)
TOP VIEW
2
4667 drw 02


Part Number IDT72V3640
Description 3.3 VOLT HIGH-DENSITY SUPERSYNC II 36-BIT FIFO
Maker Integrated Device Tech
Total Page 30 Pages
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