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Integrated Device Technology Electronic Components Datasheet

IDT74FCT32932-100 Datasheet

3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER

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IDT74FCT32932-100 pdf
IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CLOCK DRIVER
Integrated Device Technology, Inc.
COMMERCIDIATL 7TE4MFPCERTA3T9UR3E2R-1A0NG0ES
3.3V LOW SKEW PLL-BASED
IDT74FCT32932-100
CMOS CLOCK DRIVER
ADVANCE INFORMATION
FEATURES:
0.5 MICRON CMOS Technology
• Guaranteed low skew
• 16 programmable frequency configurations
• 17 3-state outputs: ±24 mA FCT3932
±8 mA FCT32932
• Output configuration:
BANK1: 4 outputs
BANK2: 8 outputs
BANK3: 5 outputs
• Dedicated feedback output (Q_FB)
• Maximum output frequency: 100MHz
• VCC = 3.3V ±0.3V
• Inputs can be driven from 3.3V or 5V components
• Available in 48 SSOP, TSSOP packages
• Suited to SDRAM applications
DESCRIPTION:
The FCT3932 uses phase-lock loop technology to lock the
frequency and phase of the feedback to the input reference
clock. It provides a large number of low skew outputs that are
configurable in 16 different modes using the CNTRL 1-4
inputs. A dedicated output, Q_FB, is provided to supply the
PLL feedback and it should be connected to the FEEDBACK
input. Q_FB is located adjacent to FEEDBACK to minimize
the delay in the feedback path. In order to offset any delay in
the output path from the FCT3932 output to a receiving device,
feedback path delay should be made to match this output path
delay.
The PLL consists of the phase/frequency detector, charge
pump, loop filter and VCO. The FCT3932 requires no external
loop filter components.
The FCT3932 provides 17 outputs grouped in 3 banks with
individual 3-state control and an additional dedicated feed-
back output with no disable. Connecting Q_FB to FEEDBACK
ensures uninterrupted PLL operation when all outputs are
disabled.
Individual bank 3-state allows users to disable unused
outputs in order to limit power dissipation or minimize switch-
ing noise. It also allows users to shut down outputs in low
power modes while maintaining phase lock.
The FCT3932 provides a LOCK pin that goes high when the
device is phase-locked.
The user can bypass the PLL for testability purposes by
deasserting PLL_EN. In this "test" mode, the input frequency
is not limited to the specified range.
RSTThe FCT3932 provides an asynchronous reset input, ,
which resets all outputs. This initializes all internal registers so
that outputs start up in a known state.
APPLICATIONS:
SDRAM DIMM Clock, Caches, high speed microproces-
sors, motherboard clock distribution to DIMMs.
FUNCTIONAL BLOCK DIAGRAM
FEEDBACK
REF_IN
LOCK
Phase/Freq.
Detector
Charge
Pump &
Loop Filter
Voltage
Controlled
Oscillator
PLL_EN
01
Mux
CNTRL1-4
C
O
N
T
R
O
L
OE1
OE2
OE3
Q41-4
(BANK 1)
Q81-8
(BANK 2)
Q51-5
(BANK 3)
Q_FB
RST
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
9.9
9.9
3267 drw 01
NOVEMBER 1996
DSC-3267/2
11


Integrated Device Technology Electronic Components Datasheet

IDT74FCT32932-100 Datasheet

3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER

No Preview Available !

IDT74FCT32932-100 pdf
IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
PIN CONFIGURATIONS
VCC
Q55
CNTRL1
GND
CNTRL2
CNTRL3
VCC
CNTRL4
Q_FB
FEEDBACK
GND
REF_IN
AVCC
NC
AGND
GND
OE1
OE2
OE3
RST
GND
PLL_EN
LOCK
VCC
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 SO48-1 37
SO48-2
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
Q54
Q53
GND
Q52
Q51
VCC
Q44
Q43
GND
Q42
Q41
VCC
VCC
Q88
Q87
GND
Q86
Q85
VCC
Q84
Q83
GND
Q82
Q81
SSOP
TSSOP
TOP VIEW
3267 drw 02
*NC = No connect
COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
VTERM(2) Terminal Voltage with Respect to
GND
VTERM(3) Terminal Voltage with Respect to
GND
VTERM(4) Terminal Voltage with Respect to
GND
TSTG Storage Temperature
Max.
–0.5 to +4.6
–0.5 to +7.0
–0.5 to VCC
+ 0.5
–65 to +150
Unit
V
V
V
°C
IOUT
DC Output Current
–60 to +60 mA
NOTES:
3267 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Output and I/O terminals.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input
VIN = 0V
3.2 5.0 pF
Capacitance
CI/O
I/O
VOUT = 0V 3.7 8.0 pF
Capacitance
NOTE:
3267 lnk 02
1. This parameter is measured at characterization but not tested.
9.9 2


Part Number IDT74FCT32932-100
Description 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
Maker Integrated Device Tech
Total Page 9 Pages
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