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Intel
Intel

STEL-2060C Datasheet Preview

STEL-2060C Datasheet

45Mbps Viterbi Decoder

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STEL-2060C pdf
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STEL-2060C/CR
Data Sheet
STEL-2060C/CR
45 Mbps
Viterbi Decoder
R



Intel
Intel

STEL-2060C Datasheet Preview

STEL-2060C Datasheet

45Mbps Viterbi Decoder

No Preview Available !

STEL-2060C pdf
www.DataSheet4U.com
FEATURES
s 45 Mbps Operating Rate
s Constraint Length K = 7
G1 = 1718 G2 = 1338
s Multiple Rates: Rate 1/2 as well as
Punctured codes at Rates 2/3 through 7/8
s Internal Depuncturing Capability at Rates
2/3, 3/4 and 7/8
s Multiple Devices can be Multiplexed to
Give Higher Data Rates
s Optimized Interface to Operate with BPSK
and QPSK Demodulators
s Auto Node Sync Capability
s Differential Decoder
s “Invert G2” Descrambler
s Internal BER Monitor and BER
Measurement Circuit
s 5.2 dB Coding Gain @10-5 BER (R = 1/2)
s 100-pin PQFP Package
s 0.5 Micron CMOS Technology
BLOCK DIAGRAM
FUNCTIONAL DESCRIPTION
Convolutional encoding and Viterbi decoding are used to
provide forward error correction (FEC) which improves
digital communication performance over a noisy link. The
STEL-2060C is a specialized product designed to perform
this specific communications related function. At the
encoder a stream of symbols is created which introduces a
high degree of redundancy. This enables accurate decoding
of the information despite a high symbol error rate resulting
from an impaired communications link.
The STEL-2060C contains a K = 7 Viterbi Decoder. The data
inputs can be in offset binary or offset signed-magnitude
formats, with 3-bit soft decision. Auto node sync is provided
for applications where symbol uncertainty can occur. Rate
2/3, 3/4, 4/5, 5/6, 6/7 and 7/8 punctured signals can be
decoded, as well as non-punctured, Rate 1/2, signals. The
polynomials and puncturing patterns used are industry
standards. Depuncturing logic is incorporated into the
decoder to provide automatic depuncturing of received data
at rates 2/3, 3/4 and 7/8 when the puncturing patterns
supported by the device are used. A BER monitor is also
provided in the device, along with a circuit for computing
the mean value of the BER over an extended period. These
circuits operate with punctured codes as well as
unpunctured. The STEL-2060C incorporates a descrambler
for signals scrambled with the “Invert G2” algorithm. (With
this method the G2 symbols are logically inverted at the
encoder. This provides a very effective level of scrambling
for the purpose of avoiding long strings of ones or zeroes in
the transmitted signal using BPSK modulation.)
DSCRAM
OBIN
PARL
LDG2
G1
3
G2 3
2
PNCG1/G2
SYMCKIN
DCLKIN
SYNC
RATE
3
EXTSEL
THRES
CHOUNT
8
8
DDIF
DATA
ADDR
WR
RD
CSEL
8
3
RESET
SYMBOL
ALIGNMENT
AND
DEPUNCTURING
CIRCUIT
BRANCH
METRIC
ASSIGNMENT
TRACEBACK
MEMORY
TIMING AND
CONTROL
DIFFERENTIAL
DECODER
µP
INTERFACE
TO ALL REGISTERS
VITERBI
DECODER
(ACS)
NODE SYNC
CONTROL
BER
MONITOR
AND
COUNTER
AUTO
OOS
DATO
ODCLK
BERR
G1ERR
G2ERR
INT
STEL-2060C
2


Part Number STEL-2060C
Description 45Mbps Viterbi Decoder
Maker Intel
Total Page 19 Pages
PDF Download
STEL-2060C pdf
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STEL-2060C pdf
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