The IA4320 FSK receiver is the counterpart of the IA4220 FSK
transmitter. It covers the unlicensed frequency bands at 315, 433, 868,
and 915 MHz. The device facilitates compliance with FCC and ETSI
The programmable PLL synthesizer determines the operating frequency,
while preserving accuracy based on the on-chip crystal-controlled
reference oscillator. The PLL’s high resolution allows for the use of
multiple channels in any of the bands.
The receiver employs the Zero-IF approach with I/Q demodulation,
allowing the use of a minimal number of external components in a typical
application. The IA4320 consists of a fully integrated multi-band PLL
synthesizer, an LNA with switchable gain, I/Q down converter mixers,
baseband filters and amplifiers, and an I/Q demodulator followed
by a data filter.
The RF VCO in the PLL performs automatic calibration, which requires
only a few microseconds. Calibration always occurs when the
synthesizer begins. If temperature or supply voltage changes
significantly, VCO recalibration can be invoked easily. Recalibration
can be initiated at any time by switching the synthesizer off and back
The LNA has 250 Ohm input impedance, which works well with the
recommended antennas. (See Application Notes available from
If the RF input of the chip is connected to 50 Ohm devices, an
external matching circuit is required to provide the correct matching
and to minimize the noise figure of the receiver.
The LNA gain (and linearity) can be selected (0, –6, –14, –20 dB
relative to the highest gain) according to RF signal strength. This is
useful in an environment with strong interferers.
The receiver bandwidth is selectable by programming the bandwidth
(BW) of the baseband filters. This allows setting up the receiver
according to the characteristics of the signal to be received.
An appropriate bandwidth can be selected to accommodate various
FSK deviation, data rate, and crystal tolerance requirements. The
filter structure is a 7-th order Butterworth low-pass with 40 dB
suppression at 2*BW frequency. Offset cancellation is accomplished
by using a high-pass filter with a cut-off frequency below 7 kHz.
Data Filtering and Clock Recovery
The output data filtering can be completed by an external capacitor
or by using digital filtering according to the final application.
Analog operation: The filter is an RC type low-pass filter and a
Schmitt-trigger (St). The resistor (10k) and the St is integrated
on the chip. An (external) capacitor can be chosen according to
the actual bit-rate. In this mode the receiver can handle up to
256 kbps data rate.
Digital operation: The data filter is a digital realization of an
analog RC filter followed by a comparator with hysteresis. In this
mode there is a clock recovery circuit (CR), which can provide
synchronized clock to the data. With this clock the received data
can fill the RX Data FIFO. The CR has three operation modes:
fast, slow, and automatic. In slow mode, its noise immunity is
very high, but it has slower settling time and requires more accurate
data timing than in fast mode. In automatic mode the CR
automatically changes between fast and slow modes. The CR starts
in fast mode, then automatically switches to slow mode after
(Only the data filter and the clock recovery use the bit-rate clock.
Therefore, in analog mode, there is no need for setting the correct
Data Validity Blocks
A digital RSSI output is provided to monitor the input signal level.
It goes high if the received signal strength exceeds a given
preprogrammed level. An analog RSSI signal is also available. The
RSSI settling time depends on the filter capacitor used.
Voltage on ARRSI pin vs. Input RF power
Input Power [dBm]
P1 -65 dBm
P2 -65 dBm
P3 -100 dBm
P4 -100 dBm