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Intersil Electronic Components Datasheet

CD54AC00 Datasheet

Quad 2-Input NAND Gate

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CD54AC00 pdf
Semiconductor
CD54AC00F3A,
CD54ACT00F3A
July 1998
Quad 2-Input NAND Gate
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The CD54AC00F3A and CD54ACT00F3A are quad 2-input
NAND gates that utilize the Harris Advanced CMOS Logic
technology.
• Exceeds 2kV ESD Protection MIL-STD-883, Method 3015
• Meets JEDEC Standard No. 20
• SCR - Latch-Up-Resistant CMOS Process and Circuit
Design
• Speed of Bipolar FAST/A/S with Significantly Reduced
Power Consumption
• Functionally and Pin-Compatible with Industry 54
Bipolar Types in the FAST, AS and S Series
• Balanced Propagation Delays
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
PKG.
NO.
CD54AC00F3A
-55 to 125 14 Ld CERDIP F14.3
CD54ACT00F3A
-55 to 125 14 Ld CERDIP F14.3
NOTE:
1. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or Harris
customer service for ordering information.
• Military Operating Temperature Range
- Ceramic (CERDIP) 54 Series: . . . . . . . . -55 to 125oC Functional Diagram
±24mA Output Drive Current, Drives 75Lines with-
out Need for Terminations
• Fan Out (Over Temperature)
- ACL Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2400
- FAST Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
- AS Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
• Balanced Noise Immunity at 30% of Supply for AC
Types
• Supply Voltage Range
- AC Types . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5V to 5.5V
- ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
Pinout
1
1A
2
1B
4
2A
2B 5
9
3B
3A 10
12
4B
13
4A
3
1Y
6
2Y
8
3Y
11
4Y
GND = 7
VCC = 14
TRUTH TABLE
INPUTS
AB
OUTPUTS
Y
1A 1
1B 2
1Y 3
2A 4
2B 5
14 VCC
13 4A
12 4B
11 4Y
10 3A
L LH
HLH
L HH
HH L
2Y 6
9 3B
GND 7
8 3Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1998
1
File Number 3876.1


Intersil Electronic Components Datasheet

CD54AC00 Datasheet

Quad 2-Input NAND Gate

No Preview Available !

CD54AC00 pdf
CD54AC00F3A, CD54ACT00F3A
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC VCC or Ground Current, ICC or IGND (Note 2) . . . . . . . . .±100mA
Thermal Information
Thermal Resistance (Typical, Note 4)
θJA (oC/W) θJC (oC/W)
CERDIP Package . . . . . . . . . . . . . . . .
80
24
Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC (Note 3)
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Slew Rate, dt/dv
AC Types
1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
4.5V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. For up to 4 outputs per device, add ±25mA for each additional output.
3. Unless otherwise specified, all voltages are referenced to ground.
4. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER
AC TYPES
High Level Input Voltage
SYMBOL
VIH
TEST
CONDITIONS
VI (V)
IO (mA)
--
VCC
(V)
1.5
3
4.5
Low Level Input Voltage VIL -
5.5
- 1.5
3
4.5
High Level Output Voltage
VOH
VIH or VIL
-0.05
-0.05
-0.05
-4
-24
5.5
1.5
3
4.5
3
4.5
-50
(Note 6, 7)
5.5
25oC
MIN MAX
-55oC TO 125oC
MIN MAX
UNITS
1.2
2.1
3.15
(Note 5)
3.85
-
-
-
-
1.4
2.9
4.4
2.58
3.94
(Note 5)
-
-
-
-
-
0.3
0.9
1.35
(Note 5)
1.65
-
-
-
-
-
-
1.2
2.1
3.15
(Note 5)
3.85
-
-
-
-
1.4
2.9
4.4
2.4
3.7
(Note 5)
3.85
-
-
-
-
0.3
0.9
1.35
(Note 5)
1.65
-
-
-
-
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
2


Part Number CD54AC00
Description Quad 2-Input NAND Gate
Maker Intersil
Total Page 4 Pages
PDF Download
CD54AC00 pdf
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