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Intersil Electronic Components Datasheet

MD82C52B Datasheet

CMOS Serial Controller Interface

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MD82C52B pdf
82C52
March 1997
CMOS Serial Controller Interface
Features
• Single Chip UART/BRG
• DC to 16MHz (1M Baud) Operation
• Crystal or External Clock Input
• On-Chip Baud Rate Generator - 72 Selectable Baud
Rates
• Interrupt Mode with Mask Capability
• Microprocessor Bus Oriented Interface
• 80C86 Compatible
• Single +5V Power Supply
• Low Power Operation . . . . . . . . . . . . . . . 1mA/MHz Typ
• Modem Interface
• Line Break Generation and Detection
• Operating Temperature Range:
- C82C52 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C52 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C52 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Description
The Intersil 82C52 is a high performance programmable
Universal Asynchronous Receiver/Transmitter (UART) and
Baud Rate Generator (BRG) on a single chip. Utilizing the
Intersil advanced Scaled SAJI IV CMOS process, the 82C52
will support data rates up to 1M baud asynchronously with a
16X clock (16MHz clock frequency).
The on-chip Baud Rate Generator can be programmed for
any one of 72 different baud rates using a single industry
standard crystal or external frequency source. A unique pre-
scale divide circuit has been designed to provide standard
RS-232-C baud rates when using any one of three industry
standard crystals (1.8432MHz, 2.4576MHz, or 3.072MHz).
A programmable buffered clock output (CO) is available and
can be programmed to provide either a buffered oscillator or
16X baud rate clock for general purpose system usage.
Ordering Information
PACKAGE
PDIP
PLCC
CERDIP
SMD#
CLCC
SMD#
TEMPERATURE
RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
1M BAUD
CP82C52
IP82C52
CS82C52
IS82C52
CD82C52
ID82C52
MD82C52/B
8501501XA
MR82C52/B
85015013A
PKG. NO.
E28.6
E28.6
N28.45
N28.45
F28.6
F28.6
F28.6
F28.6
J28.A
J28.A
Pinouts
82C52 (PDIP, CERDIP)
TOP VIEW
RD 1
WR 2
D0 3
D1 4
D2 5
D3 6
D4 7
D5 8
D6 9
D7 10
A0 11
A1 12
IX 13
OX 14
28 CSO
27 VCC
26 DR
25 SDI
24 INTR
23 RST
22 TBRE
21 CO
20 RTS
19 DTR
18 DSR
17 CTS
16 GND
15 SDO
82C52 (PLCC, CLCC)
TOP VIEW
4 3 2 1 28 27 26
D2 5
25 SDI
D3 6
24 INTR
D4 7
23 RST
D5 8
D6 9
22 TBRE
21 CO
D7 10
20 RTS
A0 11
19 DTR
12 13 14 15 16 17 18
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
5-1
File Number 2950.1


Intersil Electronic Components Datasheet

MD82C52B Datasheet

CMOS Serial Controller Interface

No Preview Available !

MD82C52B pdf
Block Diagram
D0-D7
3 - 10
RD
WR
A0
A1
CSO
IX
OX
CO
RST
INTR
1
2
11
12
28
13
14
21
23
24
DATA
BUS
BUFFER
READ/WRITE
CONTROL
LOGIC
PROGRAM-
MABLE
BOUD RATE
GENERATOR
CONTROL
LOGIC
82C52
UART
CONTROL AND
STATUS
REGISTERS
TRANSMITTER
BUFFER
REGISTER
RECEIVER
BUFFER
REGISTER
MODEM
CONTROL AND
STATUS
REGISTERS
22 TBRE
26 DR
TRANSMITTER
REGISTER
PS
15 SDO
RECEIVER
REGISTER
PS
25
SDI
18 DSR
17 CTS
19 DTR
20 RTS
Pin Description
PIN ACTIVE
SYMBOL NO. TYPE LEVEL
DESCRIPTION
RD 1 I Low READ: The RD input causes the 82C52 to output data to the data bus (D0-D7). The data
output depends upon the state of the address inputs (A0-A1). CS0 enables the RD input.
WR 2 I Low WRITE: The WR input causes data from the data bus (D0-D7) to be input to the 82C52.
Addressing and chip select action is the same as for read operations.
D0-D7
3-10 I/O
High
DATA BITS 0-7: The Data Bus provides eight, three-state input/output lines for the transfer of
data, control and status information between the 82C52 and the CPU. For character formats
of less than 8 bits, the corresponding D7, D6 and D5 are considered “don't cares” for data
WRITE operations and are 0 for data READ operations. These lines are normally in a high
impedance state except during read operations. D0 is the Least Significant Bit (LSB) and is the
first serial data bit to be received or transmitted.
A0, A1 11, 12 I
High
ADDRESS INPUTS: The address lines select the various internal registers during CPU bus
operations.
IX, OX 13, 14 I/O
CRYSTAL/CLOCK: Crystal connections for the internal Baud Rate Generator. IX can also be
used as an external clock input in which case OX should be left open.
SDO
15 O High SERIAL DATA OUTPUT: Serial data output from the 82C52 transmitter circuitry. A Mark (1) is
a logic one (high) and Space (0) is logic zero (low). SD0 is held in the Mark condition when
CTS is false, when RST is true, when the Transmitter Register is empty, or when in the Loop
Mode.
GND
16
Low GROUND: Power supply ground connection.
CTS
17 I
Low CLEAR TO SEND: The logical state of the CTS line is reflected in the CTS bit of the Modem
Status Register. Any change of state in CTS causes INTR to be set true when INTEN and
MIEN are true. A false level on CTS will inhibit transmission of data on the SD0 output and will
hold SD0 in the Mark (high) state. If CTS goes false during transmission, the current character
being transmitted will be completed. CTS does not affect Loop Mode operation.
5-2


Part Number MD82C52B
Description CMOS Serial Controller Interface
Maker Intersil
Total Page 19 Pages
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