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KODENSHI KOREA
KODENSHI KOREA

KK4001B Datasheet Preview

KK4001B Datasheet

Quad 2-Input NOR Gate High-Voltage Silicon-Gate CMOS

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TECHNICAL DATA
KK4001B
Quad 2-Input NOR Gate
High-Voltage Silicon-Gate CMOS
The KK4001B NOR gates provide the system designer with direct
emplementation of the NOR function.
Operating Voltage Range: 3.0 to 18 V
Maximum input current of 1 µA at 18 V over full package-temperature
range; 100 nA at 18 V and 25°C
Noise margin (over full package temperature range):
0.5 V min @ 5.0 V supply
1.0 V min @ 10.0 V supply
1.5 V min @ 15.0 V supply
ORDERING INFORMATION
KK4001BN Plastic
KK4001BD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 14 =VCC
PIN 7 = GND
FUNCTION TABLE
Inputs
AB
LL
LH
HL
HH
Output
Y
H
L
L
L
L – LOW voltage level
H – HIGH voltage level
1



KODENSHI KOREA
KODENSHI KOREA

KK4001B Datasheet Preview

KK4001B Datasheet

Quad 2-Input NOR Gate High-Voltage Silicon-Gate CMOS

No Preview Available !

KK4001B pdf
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KK4001B
MAXIMUM RATINGS*
Symbol
Parameter
Value
VCC DC Supply Voltage (Referenced to GND)
VIN DC Input Voltage (Referenced to GND)
IIN DC Input Current, per Pin
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
-0.5 to +20
-0.5 to VCC +0.5
±10
500
500
Ptot Power Dissipation per Output Transistor
100
Tstg Storage Temperature
-65 to +150
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 12 mW/°C from 100° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
Unit
V
V
mA
mW
mW
°C
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
VIN, VOUT
TA
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Min Max Unit
3.0 18
V
0 VCC V
-55 +125
°C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or
VOUT)VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2


Part Number KK4001B
Description Quad 2-Input NOR Gate High-Voltage Silicon-Gate CMOS
Maker KODENSHI KOREA
Total Page 5 Pages
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