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KODENSHI KOREA
KODENSHI KOREA

KK4030B Datasheet Preview

KK4030B Datasheet

Quad Exclusive-OR Gate High-Voltage Silicon-Gate CMOS

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KK4030B pdf
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Quad Exclusive-OR Gate
High-Voltage Silicon-Gate CMOS
TECHNICAL DATA
KK4030B
The KK4030B types consist of four independent Exclusive-OR gates.
The KK4030B provides the system designer with a means for direct
implementation of the Exlusive-OR function.
Operating Voltage Range: 3.0 to 18 V
Maximum input current of 1 µA at 18 V over full package-temperature
range; 100 nA at 18 V and 25°C
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
KK4030BN Plastic
KK4030BD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 14 =VCC
PIN 7 = GND
FUNCTION TABLE
Inputs
AB
LL
LH
HL
HH
Output
Y
L
H
H
L
1



KODENSHI KOREA
KODENSHI KOREA

KK4030B Datasheet Preview

KK4030B Datasheet

Quad Exclusive-OR Gate High-Voltage Silicon-Gate CMOS

No Preview Available !

KK4030B pdf
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KK4030B
MAXIMUM RATINGS*
Symbol
Parameter
Value
VCC
VIN
VOUT
IIN
PD
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
-0.5 to +20
-0.5 to VCC +0.5
-0.5 to VCC +0.5
±10
750
500
PD Power Dissipation per Output Transistor
Tstg Storage Temperature
100
-65 to +150
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
Unit
V
V
V
mA
mW
mW
°C
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
TA
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Min Max Unit
3.0 18
V
0 VCC V
-55 +125
°C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or
VOUT)VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2


Part Number KK4030B
Description Quad Exclusive-OR Gate High-Voltage Silicon-Gate CMOS
Maker KODENSHI KOREA
Total Page 5 Pages
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