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KODENSHI KOREA
KODENSHI KOREA

KK4043B Datasheet Preview

KK4043B Datasheet

Quad 3-State R/S Latches High-Voltage Silicon-Gate CMOS

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KK4043B pdf
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Quad 3-State R/S Latches
High-Voltage Silicon-Gate CMOS
TECHNICAL DATA
KK4043B
The KK4043B types are quad cross-coupled 3-state CMOS NOR
latces. Each latch has a separate Q output and individual SET and RESET
inputs. The Q outputs are controlled by a common ENABLE input. A
logic “1” or high on the ENABLE input connects the latch states to the Q
outputs. A logic “0” or low on the ENABLE input disconnects the latch
states from the Q outputs, resulting in an open circuit condition on the Q
outputs. The open circuit feature allows common busing of the outputs.
Operating Voltage Range: 3.0 to 18 V
Maximum input current of 1 µA at 18 V over full package-temperature
range; 100 nA at 18 V and 25°C
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
KK4043BN Plastic
KK4043BD SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 13 = NO CONNECTION
PIN 16=VCC
PIN 8= GND
FUNCTION TABLE
Inputs
S R OE
XX L
LL
LH
HL
HH
H
H
H
H
X = don’t care
Outputs
Q
High
Impedance
No change
L
H
H
1



KODENSHI KOREA
KODENSHI KOREA

KK4043B Datasheet Preview

KK4043B Datasheet

Quad 3-State R/S Latches High-Voltage Silicon-Gate CMOS

No Preview Available !

KK4043B pdf
www.DataSheet4U.com
KK4043B
MAXIMUM RATINGS*
Symbol
Parameter
Value
VCC
VIN
VOUT
IIN
PD
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
-0.5 to +20
-0.5 to VCC +0.5
-0.5 to VCC +0.5
±10
750
500
PD Power Dissipation per Output Transistor
Tstg Storage Temperature
100
-65 to +150
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
Unit
V
V
V
mA
mW
mW
°C
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
VIN, VOUT
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA Operating Temperature, All Package Types
Min Max Unit
3.0 18
V
0 VCC V
-55 +125
°C
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND(VIN or VOUT)VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2


Part Number KK4043B
Description Quad 3-State R/S Latches High-Voltage Silicon-Gate CMOS
Maker KODENSHI KOREA
Total Page 6 Pages
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