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LS7366R Datasheet Preview

LS7366R Datasheet

32 BIT QUADRATURE COUNTER

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LS7366R pdf
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LS7366R
U
®
L
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405
A3800
32-BIT QUADRATURE COUNTER WITH SERIAL INTERFACE
GENERAL FEATURES:
• Operating voltage: 3V to 5.5V (VDD - VSS)
• 5V count frequency: 40MHz
• 3V count frequency: 20MHz
• 32-bit counter (CNTR).
• 32-bit data register (DTR) and comparator.
• 32-bit output register (OTR).
• Two 8-bit mode registers (MDR0, MDR1)
for programmable functional modes.
• 8-bit instruction register (IR).
• 8-bit status register (STR).
• Latched Interrupt output on Carry or Borrow or Compare or Index.
• Index driven counter load, output register load or counter reset.
• Internal quadrature clock decoder and filter.
• x1, x2 or x4 mode of quadrature counting.
• Non-quadrature up/down counting.
• Modulo-N, Non-recycle, Range-limit or
Free-running modes of counting
• 8-bit, 16-bit, 24-bit and 32-bit programmable configuration
synchronous (SPI) serial interface
• LS7366R (DIP), LS7366R-S (SOIC), LS7366R-TS (TSSOP)
- See Figure 1 -
SPI/MICROWIRE (Serial Peripheral Interface):
• Standard 4-wire connection: MOSI, MISO, SS/ and SCK.
• Slave mode only.
GENERAL DESCRIPTION:
LS7366R is a 32-bit CMOS counter, with direct interface for quadra-
ture clocks from incremental encoders. It also interfaces with the
index signals from incremental encoders to perform variety of
marker functions.
For communications with microprocessors or microcontrollers, it
provides a 4-wire SPI/MICROWIRE bus.The four standard bus I/Os
are SS/, SCK, MISO and MOSI. The data transfer between a micro-
controller and a slave LS7366R is synchronous. The synchroniza-
tion is done by the SCK clocks supplied by the microcontroller. Each
transmission is organized in blocks of 1 to 5 bytes of data. A trans-
mission cycle is intitiated by a high to low transition of the SS/ input.
The first byte received in a transmission cycle is always an instruc-
tion byte, whereas the second through the fifth bytes are always
interpreted as data bytes. A transmission cycle is terminated with
the low to high transition of the SS/ input. Received bytes are shifted
in at the MOSI input, MSB first, with the leading edges (high transi-
tion) of the SCK clocks. Output data are shifted out on the MISO
output, MSB first, with the trailing edges (low transition) of the SCK
clocks.
May 2006
PIN ASSIGNMENT
TOP VIEW
f CKO 1
f CKi 2
Vss 3
SS/ 4
SCK 5
MISO 6
MOSI 7
FIGURE 1
14 V DD
13 CNT_EN
12 A
11 B
10 INDEX/
9 DFLAG/
8 LFLAG/
Read and write commands cannot be combined.
For example, when the device is shifting out read
data on MISO output, it ignores the MOSI input,
even though the SS/ input is active. SS/ must be
terminated and reasserted before the device will
accept a new command.
The counter can be configured to operate as 1, 2, 3
or 4-byte counter. When configured as an n-byte
counter, the CNTR, DTR and OTR are all config-
ured as n-byte registers, where n = 1, 2, 3 or 4.
The content of the instruction/data identity is
automatically adjusted to match the n-byte configu-
ration. For example, if the counter is configured as a
2-byte counter, the instruction “write to DTR”
expects 2 data bytes following the instruction byte.
If the counter is configured as a 3-byte counter, the
same instruction will expect 3 bytes of data follow-
ing the instruction byte.
Following the transfer of the appropriate number of
bytes any further attempt of data transfer is ignored
until a new instruction cycle is started by switching
the SS/ input to high and then low.
The counter can be programmed to operate in a
number of different modes, with the operating
characteristics being written into the two mode
registers MDR0 and MDR1. Hardware I/Os are
provided for event driven operations, such as
processor interrupt and index related functions.
7366R-050106-1



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LS7366R Datasheet Preview

LS7366R Datasheet

32 BIT QUADRATURE COUNTER

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LS7366R pdf
I/O Pins:
Following is a description of all the input/output pins.
A (Pin 12) B (Pin 11)
Inputs. A and B quadrature clock outputs from incremental
encoders are directly applied to the A and B inputs of the
LS7366R. These clocks are ideally 90 degrees out-of-phase
signals. A and B inputs are validated by on-chip digital filters
and then decoded for up/down direction and count clocks.
In non-quadrature mode, A serves as the count input and B
serves as the direction input (B = high enables up count,
B = low enables down count). In non-quadrature mode,
the A and B inputs are not filtered internally, and are instan-
taneous in nature.
INDEX/ (Pin 10)
Input. The INDEX/ is a programmable input that can be
driven directly by the Index output of an incremental encod-
er. It can be programmed via the MDR0 to function as one
of the following:
LCNTR (load CNTR with data from DTR), RCNTR (reset
CNTR), or LOTR (load OTR with data from CNTR).
Alternatively, the INDEX input can be masked out for "no
functionality".
In quadrature mode, the INDEX/ input can be configured to
operate in either synchronous or asynchronous mode. In the
synchronous mode the INDEX/ input is sampled with the
same filter clock used for sampling the A and the B inputs
and must satisfy the phase relationship in which the INDEX/
is in the active level of Logic 0 during a minimum of a
quarter cycle of both A and B High or both A and B Low. In
non-quadrature mode, the INDEX/ input is unconditionally
set to the asynchronous mode. In the asynchronous mode,
the INDEX/ input is not sampled and can be applied in any
phase relationship with respect to A and B.
fCKi (Pin 2), fCK0 (Pin 1)
Input, Output. A crystal connected between these 2 pins
generates the basic clock for filtering the A, B and INDEX/
inputs in the quadrature count mode. Instead of a crystal the
fCKi input may also be driven by an external clock.
The frequency at the fCKi input is either divided by 2
(if MDR0 <B7> = 1) or divided by 1 (if MDR0 <B7> = 0) for
the filter circuit. For proper filtering of the A, B and the Index/
inputs the following condition must be satisfied:
ff 4fQA
Where ff is the internal filter clock frequency derived from the
fCKi in accordance with the status of MDR0 <B7> and fQA is
the maximum frequency of Clock A in quadrature mode. In
non-quadrature count mode, fCKi is not used and should be
tied off to any stable logic state.
SS/ (Pin 4)
A high to low transition at the SS/ (Slave Select) input
selects the LS7366R for serial bi-directional data transfer; a
low to high transition disables serial data transfer and brings
the MISO output to high impedance state. This allows for the
accommodation of multiple slave units on the serial I/O.
CNT_EN (Pin 13)
Input. Counting is enabled when CNT_EN input is high; counting
is disabled when this input is low. There is an internal pull-up
resistor on this input.
LFLAG/ (Pin 8), DFLAG/ (Pin 9)
Outputs. LFLAG/ and DFLAG/ are programmable outputs to flag
the occurences of Carry (counter overflow), Borrow (counter
underflow), Compare (CNTR = DTR) and INDEX. The LFLAG/ is
an open drain latched output. In contrast, the DFLAG/ is a push-
pull instantaneous output. The LFLAG/ can be wired in multi-
slave configuration, forming a single processor interrupt line.
When active LFLAG/ switches to logic 0 and can be restored to
the high impedence state only by clearing the status register,
STR. In contrast, the DFLAG/ dynamically switches low with
occurences of Carry, Barrow, Compare and INDEX conditions.
The configuration of LFLAG/ and DFLAG/ are made through the
control register MDR1.
MOSI (RXD) (Pin 7)
Input. Serial output data from the host processor is shifted into
the LS7366R at this input.
MISO (TXD) (Pin 6)
Output. Serial output data from the LS7366R is shifted out on
the MISO (Master In Slave Out) pin. The MISO output goes into
high impedance state when SS/ input is at logic high, providing
multiple slave-unit serial outputs to be wire-ORed.
SCK (Pin 5)
Input. The SCK input serves as the shift clock input for transmit-
ting data in and out of LS7366R on the MOSI and the MISO
pins, respectively. Since the LS7366R can operate only in the
slave mode, the SCK signal is provided by the host processor
as a means for synchronizing the serial transmission between
itself and the slave LS7366R.
REGISTERS:
The following is a list of LS7366 internal registers:
Upon power-up the registers DTR, CNTR, STR, MDR0 and
MDR1 are reset to zero.
DTR. The DTR is a software configurable 8, 16, 24 or 32-bit
input data register which can be written into directly from MOSI,
the serial input. The DTR data can be transferred into the 32-bit
counter (CNTR) under program control or by hardware index
signal. The DTR can be cleared to zero by software control. In
certain count modes, such as modulo-n and range-limit, DTR
holds the data for "n" and the count range, respectively. In
compare operations, whereby compare flag is set, the DTR is
compared with the CNTR.
7366R-050106-2


Part Number LS7366R
Description 32 BIT QUADRATURE COUNTER
Maker LSI
Total Page 13 Pages
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