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Lattice Semiconductor
Lattice Semiconductor

5962-89841 Datasheet Preview

5962-89841 Datasheet

Microcircuit / Memory / CMOS

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5962-89841 pdf
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REVISIONS
LTR DESCRIPTION
A Added K package. Added 04 device, two suppliers and 05 device,
one supplier. Added vendor CAGE 34335 for devices 01L, 013, and
02L. Editorial changes throughout. Added vendor CAGE 34335 for
devices 01K, 023, and 02K. Redrawn.
B Added vendor CAGE 65786 for devices 01, 02, 03, 04, and 05LX,
KX, and 3X. Added vendor CAGE 18324 for devices 01, 02, 04, and
05LX. IAW NOR 5962-R079-93.
C Added 06 device for one supplier. Added test tSU2 to table I.
Editorial changes throughout. Redrawn.
D Added devices 07-14, Added CAGE 1FN41 for devices 13 and 14,
added test ICCSB to table I for devices 13 and 14, and updated text to
newer boiler plate.
E Changes in accordance with NOR 5962-R263-97
F Changes in accordance with NOR 5962-R341-97
G Added powerup-reset parameters to table I, and the waveform as
figure 5. Updated boilerplate. ksr
H Changed minimum IOS value for devices 01 thru 06 on table I.
Value was changed from -50 mA to -30 mA. ksr
J Updated boiler plate. ksr
DATE (YR-MO-DA)
91 – 04 – 19
93 – 01 – 28
93 – 07 – 30
97 – 03 – 04
97 – 04 – 23
97 – 06 – 05
98 – 07 – 10
99 – 03 – 19
02 - 10 - 10
APPROVED
M. A. Frye
M. A. Frye
M. A. Frye
Raymond Monnin
Raymond Monnin
Raymond Monnin
Raymond Monnin
Raymond Monnin
Raymond Monnin
REV
SHEET
REV
JJJ
SHEET
15 16 17
REV STATUS
OF SHEETS
REV
SHEET
JJJJJJJJJJJJJ J
1 2 3 4 5 6 7 8 9 10 11 12 13 14
PMIC N/A
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF
DEFENSE
PREPARED BY
Kenneth Rice
CHECKED BY
Charles Reusing
APPROVED BY
Michael A. Frye
DRAWING APPROVAL DATE
89 – 11 – 28
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216
http://www.dscc.dla.mil
MICROCIRCUIT, MEMORY, DIGITAL,
CMOS, PROGRAMMABLE ARRAY
LOGIC (EEPLD), MONOLITHIC
SILICON
AMSC N/A
REVISION LEVEL
J
SIZE
A
CAGE CODE
67268
5962-89841
SHEET
DSCC FORM 2233
APR 97
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
1 OF 17
5962-E540-02



Lattice Semiconductor
Lattice Semiconductor

5962-89841 Datasheet Preview

5962-89841 Datasheet

Microcircuit / Memory / CMOS

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5962-89841 pdf
www.DataSheet4U.com
1. SCOPE
1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits
in accordance with MIL-PRF-38535, appendix A.
1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example:
5962-89841
01
KX
Drawing number
Device type
(see 1.2.1)
Case outline
(see 1.2.2)
Lead finish
(see 1.2.3)
1.2.1 Device type(s). The device type(s) shall identify the circuit function as follows:
Device type
Generic number
Circuit function
Access time
01, 07
02, 08
03, 09
04, 10
05, 11
06, 12
13
14
22V10
22V10
22V10
22V10
22V10
22V10
22V10L
22V10L
22-input, 10-output, EECMOS, architecturally
generic, programmable AND-OR array
22-input, 10-output, EECMOS, architecturally
generic, programmable AND-OR array
22-input, 10-output, EECMOS, architecturally
generic, programmable AND-OR array
22-input, 10-output, EECMOS, architecturally
generic, programmable AND-OR array
22-input, 10-output, EECMOS, architecturally
generic, programmable AND-OR array (higher tCO,
lower fCLK2)
22-input, 10-output, EECMOS, architecturally
generic, programmable AND-OR array
22-input, 10-output, EECMOS, architecturally
generic, programmable AND-OR array
22-input, 10-output, EECMOS, architecturally
generic, programmable AND-OR array
30
20
15
25
15
10
25
20
1.2.2 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows:
Outline letter
K
L
3
Descriptive designator
GDFP2-F24 or CDFP3-F24
GDIP3-T24 or CDIP4-T24
CQCC1-N28
Terminals
24
24
28
Package style
flat pack
dual-in-line
square chip carrier
1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A.
1.3 Absolute maximum ratings.
Supply voltage range ------------------------------------------------------- -0.5 V dc to +7.0 V dc
Input voltage applied ------------------------------------------------------ -0.5 V dc to VCC +1.0 V dc 1/
Off-state output voltage applied ----------------------------------------- -0.5 V dc to VCC +1.0 V dc 1/
Storage temperature range (TSTG) ------------------------------------ -65°C to +150°C
Maximum power dissipation (PD) 2/ ----------------------------------- 1.5 W
Lead temperature (soldering, 10 seconds) (TSOL) ---------------- +260°C
Thermal resistance, junction-to-case (ΘJC) ------------------------- See MIL-STD-1835
Junction temperature (TJ) ------------------------------------------------- +175°C
Data retention----------------------------------------------------------------- 10 years (minimum)
Endurance -------------------------------------------------------------------- 100 erase/write cycles (minimum)
_______________
1/ Minimum voltage is -0.5 V which may undershoot to -2.5 V for pulses of less than 20 ns.
2/ Must withstand the added PD due to short circuit test; e.g., IOS.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
J
5962-89841
SHEET
2


Part Number 5962-89841
Description Microcircuit / Memory / CMOS
Maker Lattice Semiconductor
Total Page 21 Pages
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