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Micrel Semiconductor
Micrel Semiconductor

SY89250V Datasheet Preview

SY89250V Datasheet

ENHANCED DIFFERENTIAL RECEIVER

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SY89250V pdf
Micrel, Inc.
ENHANCED DIFFERENTIAL
RECEIVER
Precision Edge®
Precision ESYd8g9e2®50V
SY89250V
FEATURES
s 3.3V and 5V power supply options
s 250ps propagation delay
Precision Edge®
s Very high voltage gain
s Ideal for Pulse Amplifier and Limiting Amplifier
DESCRIPTION
applications
s Data synchronous Enable/Disable (/EN) on QHG and
/QHG provides for complete glitchless gating of the
outputs
s Ideal for gating timing signals
The SY89250V is a differential PECL/ECL receiver/buffer
in a space saving (2mm × 2mm) MLF™ package. The device
is functionally equivalent to the SY100EL16VC, but features
a 70% smaller footprint. It provides a VBB output for either
single-ended application or as a DC bias for AC-coupling to
s Complete solution for high quality, high frequency
crystal oscillator applications
s Available in an ultra-small 8-pin (2mm × 2mm)
MLF™ package
the device.
The SY89250V provides an /EN input which is synchro-
nized with the data input (D) signal in a way that provides
glitchless gating of the QHG and /QHG outputs. When the /EN
signal is LOW, the input is passed to the outputs and the data
output equals the data input. When the data input is HIGH and
the /EN goes HIGH, it will force the QHG LOW and the /QHG
HIGH on the next negative transition of the data input. If the
data input is LOW when the /EN goes HIGH, the next data
APPLICATIONS
s Oscillator modules
transition to a HIGH is ignored and QHG remains LOW and
/QHG remains HIGH. The next positive transition of the data
inputwww.DataSheet4U.com is not passed on to the data outputs under these
conditions. The QHG and /QHG outputs remain in their dis-
abled state as long as the /EN input is held HIGH. The /EN
input has no influence on the /Q output and the data input is
passed on (inverted) to this output whether /EN is HIGH or
LOW. This configuration is ideal for crystal oscillator applica-
tions, where the oscillator can be free running and gated on
and off synchronously without adding extra counts to the
output.
All support documentation can be found on Micrel’s web
site at www.micrel.com.
BLOCK DIAGRAM
FUNCTIONAL CROSS REFERENCE
/Q 1
D2
VBB 3
OE
VBB LEN Q
/EN 4
LATCH
D
8 VCC
7 QHG
6 /QHG
5 VEE
Micrel Part Number PECL/ECL
SY89250V
100k
Functional Cross
SY100EL16VC
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc.
M9999-052505
hbwhelp@micrel.com or (408) 955-1690
1
Rev.: B Amendment: /0
Issue Date: May 2005



Micrel Semiconductor
Micrel Semiconductor

SY89250V Datasheet Preview

SY89250V Datasheet

ENHANCED DIFFERENTIAL RECEIVER

No Preview Available !

SY89250V pdf
Micrel, Inc.
Precision Edge®
SY89250V
PACKAGE/ORDERING INFORMATION
/Q
D
VBB
/EN
1
2
3
4
8 VCC
7 QHG
6 /QHG
5 VEE
8-Pin MLF™
(Ultra-Small Outline)
Ordering Information(1)
Part Number
SY89250VMI
SY89250VMITR(2)
SY89250VMG
Package
Type
MLF-8
MLF-8
MLF-8
Operating
Range
Industrial
Industrial
Industrial
SY89250VMGTR(2) MLF-8
Industrial
Package
Marking
250
250
250 with
Pb-Free bar-line indicator
250 with
Pb-Free bar-line indicator
Lead
Finish
Sn-Pb
Sn-Pb
Pb-Free
NiPdAu
Pb-Free
NiPdAu
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only.
2. Tape and Reel.
PIN DESCRIPTION
Pin Number
1
2
3
4
5
6, 7
8
Pin Name
/Q
D
Type
100k
100k
VBB
/EN
Reference
Output Voltage
Enable Input
VEE,
Exposed Pad
/QHG, QHG
Negative
Power Supply
100k
ECL Output
VCC
Positive
Power Supply
Pin Function
Single-Ended PECL/ECL Feedback Output.
Single-Ended PECL/ECL Input: The signal input includes an internal 75k
pull-down ECL Input resistor. If input is left open, Q output will default to
LOW. See Input Interface Applicationssection for single-ended inputs.
Bias Voltage: VCC1.3V. Used as reference voltage when AC-coupling to
the D input. Max sink/source is ±0.5mA.
/EN Input which is synchronized with data input (D) signal in a way that
provides glitchless gating of QHG and /QHG outputs. Includes internal 75k
pull-down resistor. Default is LOW
Negative Power Supply: VEE and exposed pad must be tied to most
negative supply. For PECL/LVPECL connect to ground.
Differential PECL/ECL Output: Defaults to LOW if D inputs left open.
See Output Interface Applicationssection for recommendations on
terminations.
Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors.
TRUTH TABLE
/EN QHG Output
0 Data
1 Logic Low
M9999-052505
hbwhelp@micrel.com or (408) 955-1690
2


Part Number SY89250V
Description ENHANCED DIFFERENTIAL RECEIVER
Maker Micrel Semiconductor
Total Page 6 Pages
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