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MT18LD272A Datasheet Preview

MT18LD272A Datasheet

(MT18LD272A / MT18LD472A) NONBUFFERED DRAM DIMMs

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MT18LD272A pdf
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OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
DRAM
MODULE
MT9LD272A(X), MT18LD472A(X)
For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/mti/msp/html/datasheet.html
FEATURES
• JEDEC-standard, eight-CAS#, ECC pinout in a 168-pin,
dual in-line memory module (DIMM)
• 16MB (2 Meg x 72) and 32MB (4 Meg x 72)
• Nonbuffered
• High-performance CMOS silicon-gate process
• Single +3.3V ±0.3V power supply
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR) and HIDDEN
• 2,048-cycle refresh distributed across 32ms
• FAST-PAGE-MODE (FPM) or Extended Data-Out
(EDO) PAGE MODE access cycles
• Serial presence-detect (SPD)
OPTIONS
• Package
168-pin DIMM (gold)
• Timing
50ns access
60ns access
• Access Cycles
FAST PAGE MODE
EDO PAGE MODE
*EDO version only
MARKING
G
-5*
-6
None
X
KEY TIMING PARAMETERS
EDO Operating Mode
SPEED
-5
-6
tRC
84ns
104ns
tRAC
50ns
60ns
tPC
20ns
25ns
tAA
25ns
30ns
tCAC
13ns
15ns
tCAS
8ns
10ns
FPM Operating Mode
SPEED tRC
tRAC
-6 110ns 60ns
tPC
35ns
tAA
30ns
tCAC
15ns
tRP
40ns
NOTE: Pin symbols in parentheses are not used on these modules but may be used
for other modules in this product family. They are for reference only.
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
1
PIN ASSIGNMENT (Front View)
168-Pin DIMM
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1 VSS 43 VSS 85 VSS 127 VSS
2 DQ0 44 OE2# 86 DQ32 128 RFU
3 DQ1 45 RAS2# 87 DQ33 129 NC/RAS3#*
4 DQ2 46 CAS2# 88 DQ34 130 CAS6#
5 DQ3 47 CAS3# 89 DQ35 131 CAS7#
6 VDD 48 WE2# 90 VDD 132 RFU
7 DQ4 49 VDD 91 DQ36 133 VDD
8
DQ5 50
NC
92 DQ37 134
NC
9
DQ6 51
NC
93 DQ38 135
NC
10 DQ7 52 CB2 94 DQ39 136 CB6
11 DQ8 53 CB3 95 DQ40 137 CB7
12 VSS 54 VSS 96 VSS 138 VSS
13 DQ9 55 DQ16 97 DQ41 139 DQ48
14 DQ10 56 DQ17 98 DQ42 140 DQ49
15 DQ11 57 DQ18 99 DQ43 141 DQ50
16 DQ12 58 DQ19 100 DQ44 142 DQ51
17 DQ13 59
VDD 101 DQ45 143 VDD
18 VDD 60 DQ20 102 VDD 144 DQ52
19 DQ14 61
NC 103 DQ46 145 NC
20 DQ15 62
RFU 104 DQ47 146 RFU
21 CB0 63
NC 105 CB4 147 NC
22 CB1 64 VSS 106 CB5 148 VSS
23 VSS 65 DQ21 107 VSS 149 DQ53
24 NC 66 DQ22 108 NC 150 DQ54
25 NC 67 DQ23 109 NC 151 DQ55
26 VDD 68 VSS 110 VDD 152 VSS
27 WE0# 69 DQ24 111 RFU 153 DQ56
28 CAS0# 70 DQ25 112 CAS4# 154 DQ57
29 CAS1# 71 DQ26 113 CAS5# 155 DQ58
30 RAS0# 72 DQ27 114 NC 156 DQ59
31 OE0# 73
VDD 115 RFU 157 VDD
32 VSS 74 DQ28 116 VSS 158 DQ60
33 A0 75 DQ29 117 A1 159 DQ61
34 A2 76 DQ30 118 A3 160 DQ62
35 A4 77 DQ31 119 A5 161 DQ63
36 A6 78 VSS 120 A7 162 VSS
37 A8 79 NC 121 A9 163 NC
38 A10 80
NC 122 NC (A11) 164 NC
39 NC (A12) 81
NC 123 NC (A13) 165 SA0
40 VDD 82 SDA 124 VDD 166 SA1
41 VDD 83 SCL 125 RFU 167 SA2
42 RFU 84 VDD 126 RFU 168 VDD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.



Micron Technology
Micron Technology

MT18LD272A Datasheet Preview

MT18LD272A Datasheet

(MT18LD272A / MT18LD472A) NONBUFFERED DRAM DIMMs

No Preview Available !

MT18LD272A pdf
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
PART NUMBERS
EDO Operating Mode
PART NUMBER
MT9LD272AG-5 X
MT9LD272AG-6 X
MT18LD472AG-5 X
MT18LD472AG-6 X
CONFIGURATION
2 Meg x 72 ECC
2 Meg x 72 ECC
4 Meg x 72 ECC
4 Meg x 72 ECC
FPM Operating Mode
PART NUMBER
MT9LD272AG-6
MT18LD472AG-6
CONFIGURATION
2 Meg x 72 ECC
4 Meg x 72 ECC
SPEED
50ns
60ns
50ns
60ns
SPEED
60ns
60ns
GENERAL DESCRIPTION
The MT9LD272A(X) and MT18LD472A(X) are randomly
accessed 16MB and 32MB memories organized in a x72
configuration. They are specially processed to operate from
3V to 3.6V for low-voltage memory systems.
During READ or WRITE cycles, each bit is uniquely
addressed through the 21/22 address bits, which are en-
tered 11 bits (A0 -A10) at RAS# time and 10/11 bits (A0-
A10) at CAS# time.
READ and WRITE cycles are selected with the WE#
input. A logic HIGH on WE# dictates read mode, while a
logic LOW on WE# dictates write mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE# or
CAS#, whichever occurs last. An EARLY WRITE occurs
when WE# is taken LOW prior to CAS# falling. A LATE
WRITE or READ-MODIFY-WRITE occurs when WE# falls
after CAS# was taken LOW. During EARLY WRITE cycles,
the data-outputs (Q) will remain High-Z regardless of the
state of OE#. During LATE WRITE or READ-MODIFY-
WRITE cycles, OE# must be taken HIGH to disable the data-
outputs prior to applying input data. If a LATE WRITE or
READ-MODIFY-WRITE is attempted while keeping OE#
LOW, no WRITE will occur, and the data-outputs will drive
read data from the accessed location.
FAST PAGE MODE
FAST-PAGE-MODE operations allow faster data opera-
tions (READ or WRITE) within a row-address-defined
page boundary. The FAST-PAGE-MODE cycle is always
initiated with a row address strobed in by RAS#, followed
by a column address strobed in by CAS#. Additional col-
umns may be accessed by providing valid column
addresses, strobing CAS# and holding RAS# LOW , thus
executing faster memory cycles. Returning RAS# HIGH
terminates the FAST-PAGE-MODE operation.
EDO PAGE MODE
EDO PAGE MODE, designated by the “X” version, is an
accelerated FAST-PAGE-MODE cycle. The primary advan-
tage of EDO is the availability of data-out even after CAS#
goes back HIGH. EDO provides for CAS# precharge time
(tCP) to occur without the output data going invalid. This
elimination of CAS# output control provides for pipelined
READs.
FAST-PAGE-MODE modules have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS#. EDO-PAGE-MODE DRAMs operate like FAST-
PAGE-MODE DRAMs, except data will remain valid or
become valid after CAS# goes HIGH during READs, pro-
vided RAS# and OE# are held LOW. If OE# is pulsed while
RAS# and CAS# are LOW, data will toggle from valid data
to High-Z and back to the same valid data. If OE# is toggled
or pulsed after CAS# goes HIGH while RAS# remains
LOW, data will transition to and remain High-Z.
During an application, if the DQ outputs are wire OR’d,
OE# must be used to disable idle banks of DRAMs. Alterna-
tively, pulsing WE# to the idle banks during CAS# HIGH
time will also High-Z the outputs. Independent of OE#
control, the outputs will disable after tOFF, which is refer-
enced from the rising edge of RAS# or CAS#, whichever
occurs last. (Refer to the 4 Meg x 4 [MT4LC4M4E8] DRAM
data sheet for additional information on EDO functional-
ity.)
REFRESH
Returning RAS# and CAS# HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during
the RAS# HIGH time. Correct memory cell data is pre-
served by maintaining power and executing any RAS#
cycle (READ, WRITE) or RAS# REFRESH cycle (RAS#-
ONLY, CBR or HIDDEN) so that all combinations of RAS#
addresses (A0-A9/A10) are executed at least every tREF,
regardless of sequence. The CBR REFRESH cycle will in-
voke the internal refresh counter for automatic RAS# ad-
dressing.
SERIAL PRESENCE-DETECT OPERATION
This module family incorporates serial presence-detect
(SPD). The SPD function is implemented using a 2,048-bit
EEPROM. This nonvolatile storage device contains 256
bytes. The first 128 bytes can be programmed by Micron to
identify the module type and various DRAM organizations
and timing parameters. The remaining 128 bytes of storage
are available for use by the customer. System READ/
WRITE operations between the master (system logic) and
the slave EEPROM device (DIMM) occur via a standard IIC
bus using the DIMM’s SCL (clock) and SDA (data) signals,
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
2 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.


Part Number MT18LD272A
Description (MT18LD272A / MT18LD472A) NONBUFFERED DRAM DIMMs
Maker Micron Technology
Total Page 30 Pages
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