64Mb: x16, x32
This 64Mb SyncFlash® data sheet is divided into
to be accessed. The address bits registered coincident
two major sections. The SDRAM Interface Functional
with the READ command are used to select the starting
Description details compatibility with the SDRAM
column location for the burst access.
memory, and the Flash Memory Functional Descrip-
The 64Mb devices provide for programmable read
tion specifies the symmetrical-sectored Flash architec-
burst lengths of 1, 2, 4, or 8 locations, or the full page,
ture and functional commands.
with a burst terminate option. The x16 device features
The 64Mb SyncFlash devices are nonvolatile, elec-
an 8-word internal write buffer and the x32 features an
trically sector-erasable (Flash), programmable read-
8-Dword internal write buffer that support mode regis-
only memory containing 67,108,864 bits. Each of the
ter programmed burst write compatibility of 1, 2, 4, or 8
x16’s 16,777,216-bit banks is organized as 4,096 rows
by 256 columns by 16 bits. Each of the x32’s 16,777,216-
SyncFlash memory uses an internal pipelined archi-
bit banks is organized as 2,048 rows by 256 columns by
tecture to achieve high-speed operation.
The 64Mb devices are designed to operate in 3.3V
The 64Mb devices are organized into 16 indepen-
VCC and 1.8V VCCQ, low-power memory systems. A deep
dently erasable blocks. To ensure that critical firmware
power-down mode is provided, along with a power-
is protected from accidental erasure or overwrite, this
saving standby mode. All inputs and outputs are
device features sixteen (x32: 128K-Dword; x16: 256K-
word) hardware and software-lockable blocks.
SyncFlash memory offers substantial advances in
A four-bank architecture supports true concurrent
Flash operating performance, including the ability to
operations. A read access to any bank can occur simul-
synchronously burst data at a high data rate with auto-
taneously with a background PROGRAM or ERASE op-
matic column-address generation and the capability
eration to any other bank.
to randomly change column addresses on each clock
et4U.com SyncFlash memory has a synchronous interface (all
cycle during a burst access.
signals are registered on the positive edge of the clock
All Flash operations are performed using either a
signal, CLK). Read accesses to the memory areDbautrasSt heet4Uh.acrodmware command sequence (HCS) or a software com-
oriented; accesses start at a selected location and con-
mand sequence (SCS). The HCS operations are used
tinue for a programmed number of locations in a pro-
by memory controllers with native SyncFlash support.
grammed sequence. Accesses begin with the registra-
Standard SDRAM controllers can use SCS operation to
tion of an ACTIVE command, followed by a READ com-
perform Flash operations.
mand. The address bits registered coincident with the
Please refer to Micron’s Web site (www.micron.com/
ACTIVE command are used to select the bank and row
syncflash) for the latest data sheet.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02
DataSheet4 U .com
2 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.