2 MEG x 16 PAGE FLASH
256K x 16 SRAM COMBO MEMORY
The MT28C3224P20 and MT28C3224P18 combi-
nation Flash and SRAM memory devices provide a com-
pact, low-power solution for systems where PCB real
estate is at a premium. The dual-bank Flash devices
are high-performance, high-density, nonvolatile
memory with a revolutionary architecture that can sig-
nificantly improve system performance.
This new architecture features:
• A two-memory-bank configuration supporting
• A high-performance bus interface providing a fast
page data transfer; and
• A conventional asynchronous bus interface.
The devices also provide soft protection for blocks
by configuring soft protection registers with dedicated
command sequences. For security purposes, dual 64-
bit chip protection registers are provided.
The embedded WORD WRITE and BLOCK ERASE
functions are fully automated by an on-chip write state
machine (WSM). The WSM simplifies these operations
and relieves the system processor of secondary tasks.
An on-chip status register, one for each bank, can be
used to monitor the WSM status to determine the
progress of a PROGRAM/ERASE command.
The erase/program suspend functionality allows
compatibility with existing EEPROM emulation soft-
The devices take advantage of a dedicated power
source for the Flash memory (F_VCC) and a dedicated
power source for the SRAM memory (S_VCC), both at
1.70V–2.20V for optimized power consumption and im-
proved noise immunity. A dedicated I/O power supply
(VCCQ) is provided with an extended range (1.70V–
2.20V), to allow a direct interface to most common logic
controllers and to ensure improved noise immunity.
The separate S_VCC pin for the SRAM provides data
retention capability when required. The data reten-
tion S_VCC is specified as low as 1.0V. The
MT28C3224P20 and MT28C3224P18 devices support
two VPP voltage ranges, an in-circuit voltage of 0.9V–
2.2V and a production compatibility voltage of 12V ±5%.
The 12V ±5% VPP2 is supported for a maximum of 100
cycles and 10 cumulative hours.
The MT28C3224P20 and MT28C3224P18 devices
contain an asynchronous 4Mb SRAM organized as 256K-
words by 16 bits. These devices are fabricated using an
advanced CMOS process and high-speed/ultra-low-
power circuit technology.
The devices are packaged in a 66-ball FBGA pack-
age with 0.80mm pitch.
ARCHITECTURE AND MEMORY
The Flash memory contains two separate memory
banks (bank a and bank b) for simultaneous READ and
WRITE operations. Bank a is 8Mb deep and contains 8
x 4K-word parameter blocks and fifteen 32K-word
blocks. Bank b is 24Mb deep, is equally sectored, and
contains forty-eight 32K-word blocks.
Figures 2 and 3 show the top and bottom memory
Due to the size of the package, Micron’s standard
part number is not printed on the top of each device.
Instead, an abbreviated device mark comprised of a
five-digit alphanumeric code is used. The abbreviated
device marks are cross referenced to Micron part num-
bers in Table 1.
Cross Reference for Abbreviated Device Marks
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02
2 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.