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Micron Technology
Micron Technology

MT28C3224P20 Datasheet Preview

MT28C3224P20 Datasheet

FLASH AND SRAM COMBO MEMORY

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MT28C3224P20 pdf
FLASH AND SRAM
COMBO MEMORY
ADVANCE
2 MEG x 16 PAGE FLASH
256K x 16 SRAM COMBO MEMORY
MT28C3224P20
MT28C3224P18
Low Voltage, Extended Temperature
0.18µm Process Technology
FEATURES
• Flexible dual-bank architecture
• Support for true concurrent operations with no
latency:
Read bank b during program bank a and vice versa
Read bank b during erase bank a and vice versa
• Organization: 2,048K x 16 (Flash)
256K x 16 (SRAM)
• Basic configuration:
Flash
Bank a (8Mb Flash for data storage)
– Eight 4K-word parameter blocks
– Fifteen 32K-word blocks
Bank b (24Mb Flash for program storage)
– Forty-eight 32K-word main blocks
SRAM
4Mb SRAM for data storage
– 256K-words
• F_VCC, VCCQ, F_VPP, S_VCC voltages
MT28C3224P20
1.80V (MIN)/2.20V (MAX) F_VCC read voltage
1.80V (MIN)/2.20V (MAX) S_VCC read voltage
1.80V (MIN)/2.20V (MAX) VCCQ
MT28C3224P18
1.70V (MIN)/1.90V (MAX) F_VCC read voltage
1.70V (MIN)/1.90V (MAX) S_VCC read voltage
1.70V (MIN)/1.90V (MAX) VCCQ
MT28C3224P20/P18
1.80V (TYP) F_VPP (in-system PROGRAM/ERASE)
1.0V (MIN) S_VCC (SRAM data retention)
12V ±5% (HV) F_VPP (production programming
compatibility)
• Asynchronous access time
Flash access time: 80ns @ 1.80V F_VCC
SRAM access time: 85ns @ 1.80V S_VCC
• Page Mode read access
Interpage read access: 80ns @ 1.80V F_VCC
Intrapage read access: 30ns @ 1.80V F_VCC
• Low power consumption
• Enhanced suspend options
ERASE-SUSPEND-to-READ within same bank
PROGRAM-SUSPEND-to-READ within same bank
ERASE-SUSPEND-to-PROGRAM within same bank
• Read/Write SRAM during program/erase of Flash
• Dual 64-bit chip protection registers for security
purposes
BALL ASSIGNMENT
66-Ball FBGA (Top View)
1 2 3 4 5 6 7 8 9 10 11 12
A NC
NC A20 A11 A15 A14 A13 A12 F_VSS VccQ NC
NC
B A16 A8 A10 A9 DQ15 S_WE# DQ14 DQ7
C F_WE# NC
DQ13 DQ6 DQ4 DQ5
D S_VSS F_RP#
DQ12 S_CE2 S_VCC F_VCC
E
F_WP# F_VPP A19 DQ11
DQ10 DQ2 DQ3
F
S_LB# S_UB# S_OE#
DQ9 DQ8 DQ0 DQ1
G A18 A17 A7 A6 A3 A2 A1 S_CE1#
H NC NC F_VCC A5 A4 A0 F_CE# F_VSS F_OE# NC NC NC
Top View
(Ball Down)
• PROGRAM/ERASE cycles
100,000 WRITE/ERASE cycles per block
• Cross-compatible command set support
Extended command set
Common flash interface (CFI) compliant
OPTIONS
• Timing
80ns
85ns
• Boot Block Configuration
Top
Bottom
• Operating Voltage Range
VCC = 1.70V–1.90V
VCC = 1.80V–2.20V
• Operating Temperature Range
Commercial (0oC to +70oC)
Extended (-40oC to +85oC)
• Package
66-ball FBGA (8 x 8 grid)
MARKING
-80
-85
T
B
18
20
None
ET
FL
Part Number Example:
MT28C3224P20FL-80 BET
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02
1
©2002, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S
PRODUCTION DATA SHEET SPECIFICATIONS.



Micron Technology
Micron Technology

MT28C3224P20 Datasheet Preview

MT28C3224P20 Datasheet

FLASH AND SRAM COMBO MEMORY

No Preview Available !

MT28C3224P20 pdf
ADVANCE
2 MEG x 16 PAGE FLASH
256K x 16 SRAM COMBO MEMORY
GENERAL DESCRIPTION
The MT28C3224P20 and MT28C3224P18 combi-
nation Flash and SRAM memory devices provide a com-
pact, low-power solution for systems where PCB real
estate is at a premium. The dual-bank Flash devices
are high-performance, high-density, nonvolatile
memory with a revolutionary architecture that can sig-
nificantly improve system performance.
This new architecture features:
• A two-memory-bank configuration supporting
dual-bank operation;
• A high-performance bus interface providing a fast
page data transfer; and
• A conventional asynchronous bus interface.
The devices also provide soft protection for blocks
by configuring soft protection registers with dedicated
command sequences. For security purposes, dual 64-
bit chip protection registers are provided.
The embedded WORD WRITE and BLOCK ERASE
functions are fully automated by an on-chip write state
machine (WSM). The WSM simplifies these operations
and relieves the system processor of secondary tasks.
An on-chip status register, one for each bank, can be
used to monitor the WSM status to determine the
progress of a PROGRAM/ERASE command.
The erase/program suspend functionality allows
compatibility with existing EEPROM emulation soft-
ware packages.
The devices take advantage of a dedicated power
source for the Flash memory (F_VCC) and a dedicated
power source for the SRAM memory (S_VCC), both at
1.70V–2.20V for optimized power consumption and im-
proved noise immunity. A dedicated I/O power supply
(VCCQ) is provided with an extended range (1.70V–
2.20V), to allow a direct interface to most common logic
controllers and to ensure improved noise immunity.
The separate S_VCC pin for the SRAM provides data
retention capability when required. The data reten-
tion S_VCC is specified as low as 1.0V. The
MT28C3224P20 and MT28C3224P18 devices support
two VPP voltage ranges, an in-circuit voltage of 0.9V–
2.2V and a production compatibility voltage of 12V ±5%.
The 12V ±5% VPP2 is supported for a maximum of 100
cycles and 10 cumulative hours.
The MT28C3224P20 and MT28C3224P18 devices
contain an asynchronous 4Mb SRAM organized as 256K-
words by 16 bits. These devices are fabricated using an
advanced CMOS process and high-speed/ultra-low-
power circuit technology.
The devices are packaged in a 66-ball FBGA pack-
age with 0.80mm pitch.
ARCHITECTURE AND MEMORY
ORGANIZATION
The Flash memory contains two separate memory
banks (bank a and bank b) for simultaneous READ and
WRITE operations. Bank a is 8Mb deep and contains 8
x 4K-word parameter blocks and fifteen 32K-word
blocks. Bank b is 24Mb deep, is equally sectored, and
contains forty-eight 32K-word blocks.
Figures 2 and 3 show the top and bottom memory
organizations.
DEVICE MARKING
Due to the size of the package, Micron’s standard
part number is not printed on the top of each device.
Instead, an abbreviated device mark comprised of a
five-digit alphanumeric code is used. The abbreviated
device marks are cross referenced to Micron part num-
bers in Table 1.
Table 1
Cross Reference for Abbreviated Device Marks
PART NUMBER
MT28C3224P20FL-80 BET
MT28C3224P20FL-80 TET
MT28C3224P18FL-85 BET
MT28C3224P18FL-85 TET
PRODUCT
MARKING
FW448
FW446
FW449
FW450
SAMPLE
MARKING
FX448
FX446
FX449
FX450
MECHANICAL
SAMPLE MARKING
FY448
FY446
FY449
FY450
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02
2 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.


Part Number MT28C3224P20
Description FLASH AND SRAM COMBO MEMORY
Maker Micron Technology
Total Page 30 Pages
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