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Micron Technology
Micron Technology

MT28F322D20 Datasheet Preview

MT28F322D20 Datasheet

(MT28F322D18 / MT28F322D20) FLASH MEMORY

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MT28F322D20 pdf
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FLASH MEMORY
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
MT28F322D20
MT28F322D18
Low Voltage, Extended Temperature
0.18µm Process Technology
FEATURES
• Flexible dual-bank architecture
– Support for true concurrent operation with zero
latency
– Read bank a during program bank b and vice versa
– Read bank a during erase bank b and vice versa
• Basic configuration:
Seventy-one erasable blocks
– Bank a (8Mb for data storage)
– Bank b (24Mb for program storage)
• VCC, VCCQ, VPP voltages
– 1.70V (MIN), 1.90V (MAX) VCC, VCCQ
(MT28F322D18 only)
– 1.80V VCC, VCCQ (MIN); 2.20V VCC (MAX)and 2.25V
VCCQ (MAX) (MT28F322D20 only)
– 0.9V (TYP) VPP (in-system PROGRAM/ERASE)
– 12V ±5% (HV) VPP tolerant (factory programming
compatibility)
• Random access time: 70ns/80ns @ 1.70V VCC
• Burst Mode read access (MT28F322D20)
– MAX clock rate: 54 MHz (tCLK = 18.5ns)
– Burst latency: 70ns @ 1.80V VCC and 54 MHz
tACLK: 17ns @ 1.80V VCC and 54 MHz
• Page Mode read access1
– Eight-word page
– Interpage read access: 70ns/80ns @ 1.80V
– Intrapage read access: 30ns @ 1.80V
• Low power consumption (VCC = 2.20V)
– Asynchronous READ < 15mA (MAX)
– Standby < 50µA
– Automatic power saving feature (APS)
• Enhanced write and erase suspend options
– ERASE-SUSPEND-to-READ within same bank
– PROGRAM-SUSPEND-to-READ within same bank
– ERASE-SUSPEND-to-PROGRAM within same bank
• Dual 64-bit chip protection registers for security
purposes
• Cross-compatible command support
– Extended command set
– Common flash interface
• PROGRAM/ERASE cycle
– 100,000 WRITE/ERASE cycles per block
NOTE: 1. Data based on MT28F322D20 device.
2. A “5” in the part mark represents two different
frequencies: 54 MHz (MT28F322D20) or 52 MHz
(MT28F322D18)
BALL ASSIGNMENT
58-Ball FBGA
12345678
A A11 A8 VSS VCC VPP A18 A6 A4
B
A12 A9
A20 CLK RST# A17
A5
A3
C A13 A10
ADV# WE# A19
A7
A2
D A15 A14 WAIT# A16 DQ12 WP#
A1
E VCCQ DQ15 DQ6 DQ4 DQ2 DQ1 CE# A0
F VSS DQ14 DQ13 DQ11 DQ10 DQ9 DQ0 OE#
G DQ7 VSSQ DQ5 VCC DQ3 VCCQ DQ8 VSSQ
Top View
(Ball Down)
NOTE: See page 7 for Ball Description Table.
See page 43 for mechanical drawing.
OPTIONS
• Timing
70ns access
80ns access
• Frequency
54 MHz
40 MHz
No burst operation
• Boot Block Configuration
Top
Bottom
• Package
58-ball FBGA (8 x 7 ball grid)
• Operating Temperature Range
Extended (-40ºC to +85ºC)
MARKING
-70
-80
52
4
None
T
B
FH
ET
Part Number Example:
MT28F322D20FH-804 BET
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
1
©2002, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.



Micron Technology
Micron Technology

MT28F322D20 Datasheet Preview

MT28F322D20 Datasheet

(MT28F322D18 / MT28F322D20) FLASH MEMORY

No Preview Available !

MT28F322D20 pdf
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
GENERAL DESCRIPTION
The MT28F322D20 and MT28F322D18 are high-
performance, high-density, nonvolatile Flash memory
solutions that can significantly improve system perfor-
mance. This new architecture features a two-memory-
bank configuration that supports dual-bank operation
with no latency.
A high-performance bus interface allows a fast burst
or page mode data transfer; a conventional asynchro-
nous bus interface is provided as well.
The devices allow soft protection for blocks, as read-
only, by configuring soft protection registers with dedi-
cated command sequences. For security purposes, two
64-bit chip protection registers are provided.
The embedded WORD WRITE and BLOCK ERASE
functions are fully automated by an on-chip write state
machine (WSM). Two on-chip status registers, one for
each of the two memory partitions, can be used to moni-
tor the WSM status and to determine the progress of the
program/erase task.
The erase/program suspend functionality allows
compatibility with existing EEPROM emulation software
packages.
The devices are manufactured using 0.18µm process
technology.
Please refer to the Micron Web site (www.micron.com/
flash) for the latest data sheet.
ARCHITECTURE AND MEMORY
ORGANIZATION
The Flash devices contain two separate banks of
memory (bank a and bank b) for simultaneous READ and
WRITE operations and are available in the following bank
segmentation configuration:
• Bank a is one-fourth of the memory containing
8 x 4K-word parameter blocks, while the remainder
of bank a is split into 15 x 32K-word blocks.
• Bank b represents three-fourths of the memory, is
equally sectored, and contains 48 x 32K-word blocks.
Figures 2 and 3 show the bottom and top memory
organizations.
DEVICE MARKING
Due to the size of the package, Micron’s standard part
number is not printed on the top of each device. Instead,
an abbreviated device mark comprised of a five-digit
alphanumeric code is used. The abbreviated device marks
are cross referenced to the Micron part numbers in
Table 1.
Table 1
Cross Reference for Abbreviated Device Marks
PART NUMBER
MT28F322D20FH-705 TET
MT28F322D20FH-705 BET
MT28F322D20FH-804 TET
MT28F322D20FH-804 BET
MT28F322D18FH-705 TET
MT28F322D18FH-705 BET
MT28F322D18FH-804 TET
MT28F322D18FH-804 BET
PRODUCT
MARKING
FW546
FW547
FW548
FW549
FW558
FW559
FW543
FW542
SAMPLE
MARKING
FX546
FX547
FX548
FX549
FX558
FX559
FX543
FX542
MECHANICAL
SAMPLE MARKING
FY546
FY547
FY548
FY549
FY558
FY559
FY543
FY542
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
2 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.


Part Number MT28F322D20
Description (MT28F322D18 / MT28F322D20) FLASH MEMORY
Maker Micron Technology
Total Page 30 Pages
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