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Micron Technology
Micron Technology

MT2LDT432H Datasheet Preview

MT2LDT432H Datasheet

(MT2LDT432H / MT2LDT832H) SMALL-OUTLINE DRAM MODULE

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MT2LDT432H pdf
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SMALL-OUTLINE
DRAM MODULE
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
MT2LDT432H (X)(S), MT4LDT832H (X)(S)
For the latest data sheet, please refer to the Micron Web
site: www.micronsemi.com/datasheets/datasheet.html
FEATURES
• JEDEC pinout in a 72-pin, small-outline, dual in-
line memory module (SODIMM)
• 16MB (4 Meg x 32) and 32MB (8 Meg x 32)
PIN ASSIGNMENT (Front View)
72-Pin Small-Outline DIMM
• High-performance CMOS silicon-gate process
• Single +3.3V ±0.3V power supply
• All inputs, outputs and clocks are TTL-compatible
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) refresh
distributed across 64ms
• FAST PAGE MODE (FPM) or Extended Data-Out
(EDO) PAGE MODE access cycles
• Optional self refresh (S) for low-power data retention
1
OPTIONS
• Package
72-pin SODIMM (gold)
• Timing
50ns access
60ns access
• Access Cycles
FAST PAGE MODE
EDO PAGE MODE
• Refresh Rates
Standard Refresh
Self Refresh (128ms period)
PART NUMBERS
EDO Operating Mode
PART NUMBER
MT2LDT432HG-x X
CONFIGURATION
4 Meg x 32
MARKING
PIN FRONT PIN
1 VSS 2
G
3 DQ1 4
5 DQ3 6
7 DQ5 8
-5DataSheet4U.co191m
DQ7
PRD1
-6 13 A1
10
12
14
15 A3 16
None
17 A5 18
19 A10 20
X 21 DQ8 22
23 DQ10 24
25 DQ12 26
None
S
27 DQ14 28
29 A11 30
31 A8 32
33 NC/RAS3#* 34
35 DQ15 36
BACK
DQ0
DQ2
DQ4
DQ6
VDD
A0
A2
A4
A6
NC
DQ9
DQ11
DQ13
A7
VDD
A9
RAS2#
NC
PIN FRONT PIN
37 DQ16 38
39 VSS 40
41 CAS2# 42
43 CAS1# 44
45 NC/RAS1#* 46
47 WE# 48
49 DQ18 50
51 DQ20 52
53 DQ22 54
55 NC 56
57 DQ25 58
59 DQ28 60
61 VDD 62
63 DQ30 64
65 NC 66
67 PRD3 68
69 PRD5 70
71 PRD7 72
BACK
DQ17
CAS0#
CAS3#
RAS0#
NC (A12)
NC (A13)
DQ19
DQ21
DQ23
DQ24
DQ26
DQ27
DQ29
DQ31
PRD2
PRD4
PRD6
VSS
REFRESH
Standard
*32MB version only
NOTE: Symbols in parentheses are not used on these modules but may
be used for other modules in this product family. They are for
reference only.
MT2LDT432HG-x XS
MT4LDT832HG-x X
MT4LDT832HG-x XS
4 Meg x 32
8 Meg x 32
8 Meg x 32
Self
Standard
Self
KEY TIMING PARAMETERS
EDO Operating Mode
x = speed
SPEED tRC tRAC tPC
tAA tCAC tCAS
FPM Operating Mode
-5 84ns 50ns 20ns 25ns 13ns 8ns
-6 104ns 60ns 25ns 30ns 15ns 10ns
PART NUMBER
CONFIGURATION REFRESH
MT2LDT432HG-x
MT2LDT432HG-x S
MT4LDT832HG-x
4 Meg x 32
4 Meg x 32
8 Meg x 32
Standard
Self
Standard
FPM Operating Mode
SPEED tRC tRAC tPC
tAA tCAC tRP
MT4LDT832HG-x S
8 Meg x 32
Self
-5 90ns 50ns 30ns 25ns 13ns 30ns
x = speed
DataSheet4U.com
-6 110ns 60ns 35ns 30ns 15ns 40ns
DataShee
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
DataSheet4 U .com



Micron Technology
Micron Technology

MT2LDT432H Datasheet Preview

MT2LDT432H Datasheet

(MT2LDT432H / MT2LDT832H) SMALL-OUTLINE DRAM MODULE

No Preview Available !

MT2LDT432H pdf
www.DataSheet4U.com
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
GENERAL DESCRIPTION
The MT2LDT432H (X)(S) and MT4LDT832H (X)(S)
FAST-PAGE-MODE READ, except data will be held
are randomly accessed 16MB and 32MB memories
valid or become valid after CAS# goes HIGH, as long as
organized in a small-outline x32 configuration. They
RAS# and OE# are held LOW. (Refer to the 4 Meg x 16
are specially processed to operate from 3V to 3.6V for
[MT4LC4M16R6] DRAM data sheet for additional
low-voltage memory systems.
information on EDO functionality.)
During READ or WRITE cycles, each bit is uniquely
addressed through the address bits, which are entered
12 bits (A0-A11) at a time. RAS# is used to latch the first
12 bits and CAS# the latter 10 bits.
READ and WRITE cycles are selected with the WE#
input. A logic HIGH on WE# dictates read mode, while
a logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. If WE# goes
LOW prior to CAS# going LOW, the output pin(s)
remain open (High-Z) until the next CAS# cycle.
REFRESH
Memory cell data is retained in its correct state by
maintaining power and executing any RAS# cycle
(READ, WRITE) or RAS# refresh cycle (RAS#-ONLY,
CBR or HIDDEN) so that all combinations of RAS#
addresses are executed at least every tREF, regardless of
sequence. The CBR REFRESH cycle will invoke the
internal refresh counter for automatic RAS# address-
ing.
An optional self refresh mode is also available. The
FAST PAGE MODE
“S” option allows the user the choice of a fully static,
low-power data retention mode or a dynamic refresh
FAST-PAGE-MODE operations allow faster data
mode at the extended refresh period of 128ms. The
operations (READ or WRITE) within a row-address-
optional self refresh feature is initiated by performing
defined page boundary. The FAST-PAGE-MODE cycle
a CBR REFRESH cycle and holding RAS# LOW for the
is always initiated with a row address strobed in by
et4U.com RAS#, followed by a column address strobed in by
specified tRASS.
The self refresh mode is terminated by driving RAS# DataShee
CAS#. Additional columns may be accessed by provid-
HIGH for a minimum time of tRPS. This delay allows
ing valid column addresses, strobing CAS# and DhaotladS- heet4Ufo.crotmhe completion of any internal refresh cycles that
ing RAS# LOW, thus executing faster memory cycles.
may be in process at the time of the RAS# LOW-to-
Returning RAS# HIGH terminates the FAST-PAGE-
HIGH transition. If the DRAM controller uses a distrib-
MODE operation.
uted refresh sequence, a burst refresh is not required
upon exiting self refresh. However, if the DRAM con-
EDO PAGE MODE
EDO PAGE MODE, designated by the “X” version,
is an accelerated FAST-PAGE-MODE cycle. The pri-
mary advantage of EDO is the availability of data-out
troller utilizes a RAS#-ONLY or burst refresh sequence,
all rows must be refreshed within the average internal
refresh rate, prior to the resumption of normal opera-
tion.
even after CAS# goes back HIGH. EDO provides for
CAS# precharge time (tCP) to occur without the out-
STANDBY
put data going invalid. This elimination of CAS#
Returning RAS# and CAS# HIGH terminates a
output control provides for pipelined READs.
memory cycle and decreases chip current to a reduced
FAST-PAGE-MODE modules have traditionally
standby level. Also, the chip is preconditioned for the
turned the output buffers off (High-Z) with the rising
next cycle during the RAS# HIGH time.
edge of CAS#. EDO operates as any DRAM READ or
DataSheet4U.com
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
DataSheet4 U .com
2 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.


Part Number MT2LDT432H
Description (MT2LDT432H / MT2LDT832H) SMALL-OUTLINE DRAM MODULE
Maker Micron Technology
Total Page 25 Pages
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