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Mitsubishi
Mitsubishi

M2V28S30ATP Datasheet Preview

M2V28S30ATP Datasheet

128M Synchronous DRAM

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M2V28S30ATP pdf
SDRAM (Rev. 1.0E)
Nov. '99
MITSUBISHI LSIs
128M Synchronous DRAM
M2V28S20ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 8,388,608-WORD x 4-BIT)
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 8-BIT)
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT)
PRELIMINARY
Some of contents are described for general products and are
subject to change without notice.
DESCRIPTION
M2V28S20ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL
interface and M2V28S30ATP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40ATP is organized
as 4-bank x 2,097,152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.
M2V28S20ATP,M2V28S30ATP,M2V28S40ATP achieves very high speed data rates up to 133MHz,
and is suitable for main memory or graphic memory in computer systems.
FEATURES
ITEM
tCLK
tRAS
tRCD
tAC
tRC
Icc1
Clock Cycle Time
(Min.)
Active to Precharge Command Period
Row to Column Delay
Access Time from CLK
Ref/Active Command Period
Operation Current
(Max.)
(Single Bank)
(Min.)
(Min.)
(Max.) (CL=3)
(Min.)
V28S20
V28S30
V28S40
Icc6 Self Refresh Current
(Max.)
M2V28S20/30/40ATP
-6 -7
-8
7.5ns
10ns 10ns
45ns 50ns
50ns
20ns
5.4ns
67.5ns
20ns
6ns
70ns
20ns
6ns
70ns
100mA 95mA
95mA
110mA 100mA 100mA
130mA 120mA 120mA
2mA
2mA
2mA
- Single 3.3V ±0.3V power supply
- Max. Clock frequency -6:PC133<3-3-3> / -7:PC100<2-2-2> / -8:PC100<3-2-2>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQML and DQMU (M2V28S40ATP)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 4096 refresh cycles /64ms
- LVTTL Interface
- Package
M2V28S20ATP/30ATP/40ATP
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
MITSUBISHI ELECTRIC
1



Mitsubishi
Mitsubishi

M2V28S30ATP Datasheet Preview

M2V28S30ATP Datasheet

128M Synchronous DRAM

No Preview Available !

M2V28S30ATP pdf
SDRAM (Rev. 1.0E)
Nov. '99
MITSUBISHI LSIs
128M Synchronous DRAM
M2V28S20ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 8,388,608-WORD x 4-BIT)
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 8-BIT)
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT)
PIN CONFIGURATION (TOP VIEW)
M2V28S20ATP
M2V28S30ATP
M2V28S40ATP
Vdd
NC
VddQ
NC
DQ0
VssQ
NC
NC
VddQ
NC
DQ1
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10(AP)
A0
A1
A2
A3
Vdd
Vdd
DQ0
VddQ
NC
DQ1
VssQ
NC
DQ2
VddQ
NC
DQ3
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10(AP)
A0
A1
A2
A3
Vdd
Vdd
DQ0
VddQ
DQ1
DQ2
VssQ
DQ3
DQ4
VddQ
DQ5
DQ6
VssQ
DQ7
Vdd
DQML
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10(AP)
A0
A1
A2
A3
Vdd
PIN CONFIGURATION
(TOP VIEW)
1 54
2 53
3 52
4 51
5 50
6 49
7 48
8 47
9 46
10 45
11 44
12 43
13 42
14 41
15 40
16 39
17 38
18 37
19 36
20 35
21 34
22 33
23 32
24 31
25 30
26 29
27 28
Vss
DQ15
VssQ
DQ14
DQ13
VddQ
DQ12
DQ11
VssQ
DQ10
DQ9
VddQ
DQ8
Vss
NC
DQMU
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
Vss
DQ7
VssQ
NC
DQ6
VddQ
NC
DQ5
VssQ
NC
DQ4
VddQ
NC
Vss
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
Vss
NC
VssQ
NC
DQ3
VddQ
NC
NC
VssQ
NC
DQ2
VddQ
NC
Vss
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
CLK
CKE
/CS
/RAS
/CAS
/WE
DQ0-15
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
: Data I/O
DQM
A0-11
BA0,1
Vdd
VddQ
Vss
VssQ
: Output Disable/ Write Mask
: Address Input
: Bank Address
: Power Supply
: Power Supply for Output
: Ground
: Ground for Output
MITSUBISHI ELECTRIC
2


Part Number M2V28S30ATP
Description 128M Synchronous DRAM
Maker Mitsubishi
Total Page 30 Pages
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