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Mitsubishi
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M2V56S40AKT Datasheet Preview

M2V56S40AKT Datasheet

256M Synchronous DRAM

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M2V56S40AKT pdf
SDRAM (Rev.1.01)
Single Data Rate
July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
Some of contents are subject to change without notice.
DESCRIPTION
M2V56S20AKT is a 4-bank x 16777216-word x 4-bit,
M2V56S30AKT is a 4-bank x 8388608-word x 8-bit,
M2V56S40AKT is a 4-bank x 4194304-word x 16-bit,
synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of
CLK. The M2V56S20/30/40AKT achieve very high speed data rate up to 100MHz (-7) , 133MHz (-6),
166MHz(-5) and are suitable for main memory or graphic memory in computer systems.
FEATURES
- Single 3.3v±0.3V power supply
- Max. Clock frequency -5:PC166<3-3-3> / -6:PC133<3-3-3> / -7:PC100<2-2-2>
- Fully Synchronous operation referenced to clock rising edge
- Single Data Rate
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/full page (programmable)
- Burst type- sequential / interleave (programmable)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
- LVTTL Interface
- 10.65mm width x 13.1mm length, 64-pin STSOP(II) with 0.4mm lead pitch
M2V56S20/30/40 AKT -5
Max. Frequency
@CL2
133 MHz
M2V56S20/30/40 AKT -6
100MHz
M2V56S20/30/40 AKT -7
100 MHz
Max. Frequency
@CL3
166 MHz
133 MHz
100MHz
Standard
PC133 (CL2)
PC133 (CL3)
PC100 (CL2)
MITSUBISHI ELECTRIC
1



Mitsubishi
Mitsubishi

M2V56S40AKT Datasheet Preview

M2V56S40AKT Datasheet

256M Synchronous DRAM

No Preview Available !

M2V56S40AKT pdf
SDRAM (Rev.1.01)
Single Data Rate
July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
x4
x8
x16
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
NC
NC
VDD
NC
LDQM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32 TOP VIEW
64 VSS VSS VSS
63 DQ15 D Q 7 NC
62 VSSQ VSSQ VSSQ
61 DQ14 NC NC
60 DQ13 D Q 6 D Q 3
59 VDDQ VDDQ VDDQ
58 DQ12 NC NC
57 DQ11 D Q 5 NC
56 VSSQ VSSQ VSSQ
55 DQ10 NC NC
54 D Q 9 D Q 4 D Q 2
53 VDDQ VDDQ VDDQ
52 D Q 8 NC NC
51 NC NC NC
50 NC NC NC
49 NC NC NC
48 NC NC NC
47 VSS VSS VSS
46 UDQM D Q M D Q M
45 NC NC NC
44 CLK CLK CLK
43 CKE CKE CKE
42 NC NC NC
41 A12 A12 A12
40 A11 A11 A11
39 A9 A9 A9
38 A8 A8 A8
37 A7 A7 A7
36 A6 A6 A6
35 A5 A5 A5
34 A4 A4 A4
33 VSS VSS VSS
CLK
: Master Clock
CKE
: Clock Enable
/CS : Chip Select
/RAS
: Row Address Strobe
/CAS
: Column Address Strobe
/WE : Write Enable
DQ0-15
: Data I/O
DQM, DQMU/L : Output Disable / Write Mask
A0-12
: Address Input
BA0,1
: Bank Address Input
Vdd
: Power Supply
VddQ
: Power Supply for Output
Vss
: Ground
VssQ
: Ground for Output
MITSUBISHI ELECTRIC
2


Part Number M2V56S40AKT
Description 256M Synchronous DRAM
Maker Mitsubishi
Total Page 30 Pages
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