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Mitsubishi
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M5M417400CJ-6 Datasheet Preview

M5M417400CJ-6 Datasheet

FAST PAGE MODE DRAM

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M5M417400CJ-6 pdf
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
DESCRIPTION
This is a family of 4194304-word by 4-bit dynamic RAMS,
fabricated with the high performance CMOS process, and is ideal
for large-capacity memory systems where high speed, low power
dissipation, and low costs are essential.
The use of double-layer metal process combined with twin-well
CMOS technology and a single-transistor dynamic storage stacked
capacitor cell provide high circuit density at reduced costs.
Multiplexed address inputs permit both a reduction in pins and an
increase in system densities.
FEATURES
Type Name
M5M417400CXX-5,-5S
M5M417400CXX-6,-6S
M5M417400CXX-7,-7S
RAS
access
time
(max.ns)
50
60
70
CAS
access
time
(max.ns)
13
15
20
Address
access
time
(max.ns)
25
30
35
OE
access
time
(max.ns)
13
15
20
C ycle
time
(min.ns)
90
110
130
Power
dissipa-
tion
(typ.mW)
655
540
475
XX=J, TP
• Standard 26 pin SOJ, 26 pin TSOP
• Single 5V ± 10% supply
• Low stand-by power dissipation
5.5mW(Max) ..................................CMOS Input level
2.2mW (Max)* ...............................CMOS Input level
• Low operating power dissipation
M5M417400Cxx-5,-5S .................... 800.0mW (Max)
M5M417400Cxx-6,-6S .................... 660.0mW (Max)
M5M417400Cxx-7,-7S .................... 580.0mW (Max)
• Self refresh capability *
self refresh current ................................ 200.0 µ A(Max)
• Fast-page mode, Read-modify-write, RAS-only refresh
• CAS before RAS refresh, Hidden refresh capabilities
Early-write mode and OE to control output buffer impedance
• All inputs, output TTL compatible and low capacitance
• 2048 refresh cycles every 32ms (A0 ~ A10)
*Applicable to self refresh version (M5M417400CJ,TP-5S,-6S,
-7S :option) only
PIN DESCRIPTION
Pin name
A0 ~ A11
DQ1 ~ DQ4
RAS
CAS
W
OE
VCC
VSS
Function
Address inputs
Data inputs / outputs
Row address strobe input
Column address strobe input
Write control input
Output enable input
Power supply (+5V)
Ground (0V)
PIN CONFIGURATION (TOP VIEW)
Outline 26P0D-B (300mil SOJ)
APPLICATION
Main memory unit for computers, Microcomputer memory, Refresh
memory for CRT
Outline 26P3D-E (300mil TSOP)
NC: NO CONNECTION
1



Mitsubishi
Mitsubishi

M5M417400CJ-6 Datasheet Preview

M5M417400CJ-6 Datasheet

FAST PAGE MODE DRAM

No Preview Available !

M5M417400CJ-6 pdf
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
FUNCTION
The M5M417400CJ,TP provide, in addition to normal read, write, and read-modify-write operations, a number of other functions, e.g., fast
page mode, RAS-only refresh, and delayed-write. The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Operation
RAS
CAS
Inputs
W OE
Row
address
Read
Write (Early write)
Write (Delayed write)
ACT
ACT
ACT
ACT
ACT
ACT
NAC
ACT
ACT
ACT
DNC
DNC
APD
APD
APD
Read-modify-write
ACT
ACT
ACT
ACT
APD
RAS-only refresh
ACT
NAC
DNC
DNC
APD
Hidden refresh
ACT
ACT
NAC
ACT
APD
Self refresh
CAS before RAS refresh
Stand-by
ACT
ACT
NAC
ACT
ACT
DNC
NAC
NAC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
Note: ACT: active, NAC: nonactive, DNC: don’t care, VLD: valid, IVD: invalid, APD: applied, OPN: open
Column
address
APD
APD
APD
APD
DNC
DNC
DNC
DNC
DNC
Input/Output
Input
Output
OPN
VLD
VLD
VLD
DNC
OPN
DNC
DNC
DNC
VLD
OPN
IVD
VLD
OPN
VLD
OPN
OPN
OPN
Refresh
Remark
YES
YES
YES
YES
YES
YES
YES
YES
NO
Fast
page
mode
identical
BLOCK DIAGRAM
2


Part Number M5M417400CJ-6
Description FAST PAGE MODE DRAM
Maker Mitsubishi
Total Page 22 Pages
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