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M5M44260CJ-6S Datasheet Preview

M5M44260CJ-6S Datasheet

FAST PAGE MODE 1M-Bit DRAM

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M5M44260CJ-6S pdf
MITMSUITBSIUSBHISLHSIIsLSIs
M5MM5M444422660C0JC,TJP-,5T,-P6,--75,-,5-S6,-,6-S7,-,7S
-5S,-6S,-7S
FASFTASPTAGPAEGMEOMDOE D4E19441390443-B04IT-B(I2T62(2164241-W44O-WRODRBDY B1Y6-B16IT-B) IDTY) NDAYMNAICMRICAMRAM
DESCRIPTION
This is a family of 262144-word by 16-bit dynamic RAMs,
fabricated with the high performance CMOS process, and is ideal
for memory systems where high speed, low power dissipation, and
low costs are essential.
The use of double-layer metalization process technology and a
single-transistor dynamic storage stacked capacitor cell provide
high circuit density at reduced costs. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is small enough for
battery back-up application.
This device has 2CAS and 1W terminals with a refresh cycle of
512 cycles every 8.2ms.
FEATURES
Type name
M5M44260CXX-5,-5S
M5M44260CXX-6,-6S
M5M44260CXX-7,-7S
XX=J,TP
RAS
CAS
access access
time time
(max.ns) (max.ns)
50 13
60 15
70 20
Address OE
access access
time time
(max.ns) (max.ns)
25 13
30 15
35 20
Cycle
time
Power
dissipa-
tion
(min.ns) (typ.mW)
90 625
110 550
130 475
Standard 40pin SOJ, 44 pin TSOP (II)
Single 5V±10% supply
Low stand-by power dissipation
CMOS Input level
5.5mW (Max)
CMOS Input level
550µW (Max) *
Operating power dissipation
M5M44260Cxx-5,-5S
688mW (Max)
M5M44260Cxx-6,-6S
605mW (Max)
M5M44260Cxx-7,-7S
523mW (Max)
Self refresh capability *
Self refresh current
150µA (Max)
Extended refresh capability
Extended refresh current
150µA (Max)
Fast-page mode (512-column random access), Read-modify-write,
RAS-only refresh, CAS before RAS refresh, Hidden refresh
capabilities.
Early-write mode, LCAS / UCAS and OE to control output buffer
impedance
512 refresh cycles every 8.2ms (A0~A8)
512 refresh cycles every 128ms (A0~A8) *
Byte or word control for Read/Write operation (2CAS, 1W type)
* : Applicable to self refresh version (M5M44260CJ,TP-5S,-6S,-7S
: option) only
APPLICATION
Microcomputer memory, Refresh memory for CRT
PIN DESCRIPTION
Pin name
Function
A0~A8
Address inputs
DQ1~DQ16 Data inputs / outputs
RAS
LCAS
Row address strobe input
Lower byte control
column address strobe input
UCAS
Upper byte control
column address strobe input
W Write control input
OE Output enable input
VCC Power supply (+5V)
VSS Ground (0V)
1 M5M44260CJ,TP-5,-5S : Under development
PIN CONFIGURATION (TOP VIEW)
(5V)VCC 1
DQ1
DQ2
DQ3
2
3
4
DQ4 5
(5V)VCC 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
NC 11
NC 12
W 13
RAS 14
NC 15
A0 16
A1 17
A2 18
A3 19
(5V)VCC 20
40 VSS(0V)
39 DQ16
38 DQ15
37 DQ14
36 DQ13
35 VSS(0V)
34 DQ12
33 DQ11
32 DQ10
31 DQ9
30 NC
29 LCAS
28 UCAS
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 VSS(0V)
Outline 40P0K (400mil SOJ)
(5V)VCC 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
(5V)VCC 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
44 VSS(0V)
43 DQ16
42 DQ15
41 DQ14
40 DQ13
39 VSS(0V)
38 DQ12
37 DQ11
36 DQ10
35 DQ9
NC 13
NC 14
W 15
RAS 16
NC 17
A0 18
A1 19
A2 20
A3 21
(5V)VCC 22
32 NC
31 LCAS
30 UCAS
29 OE
28 A8
27 A7
26 A6
25 A5
24 A4
23 VSS(0V)
Outline 44P3W-R (400mil TSOP Nomal Bend)
NC: NO CONNECTION



Mitsubishi
Mitsubishi

M5M44260CJ-6S Datasheet Preview

M5M44260CJ-6S Datasheet

FAST PAGE MODE 1M-Bit DRAM

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M5M44260CJ-6S pdf
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
FUNCTION
In addition to normal read,write and read-modify-write operations
the M5M44260CJ, TP provides a number of other functions, e.g.,
fast page mode, RAS-only refresh and delayed-write. The input
conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Operation
RAS LCAS UCAS
Lower byte read
ACT ACT NAC
Upper byte read
Word read
ACT
ACT
NAC
ACT
ACT
ACT
Lower byte write
ACT ACT NAC
Upper byte write
Word write
ACT
ACT
NAC
ACT
ACT
ACT
RAS only refresh
Hidden refresh
CAS before RAS (Extended *) refresh
ACT
ACT
ACT
NAC
ACT
ACT
NAC
ACT
ACT
Self refresh *
Stand-by
ACT
NAC
ACT
DNC
ACT
DNC
Note : ACT : active, NAC : nonactive, DNC : don' t care, OPN : open
Inputs
W
NAC
NAC
NAC
ACT
ACT
ACT
DNC
DNC
DNC
DNC
DNC
OE
ACT
ACT
ACT
NAC
NAC
NAC
DNC
ACT
DNC
DNC
DNC
Row
address
APD
APD
APD
APD
APD
APD
APD
DNC
DNC
DNC
DNC
Column
address
APD
APD
APD
APD
APD
APD
DNC
DNC
DNC
DNC
DNC
Input/Output
DQ1~ DQ9~ Refresh Remark
DQ8
DQ16
DOUT OPN YES
OPN
DOUT
DIN
DNC
DOUT
DOUT
DNC
DIN
YES
YES
YES
YES
Fast
page
mode
identical
DIN DIN YES
OPN OPN YES
DOUT DOUT YES
OPN OPN YES
OPN OPN YES
OPN OPN
No
BLOCK DIAGRAM
ROW ADDRESS
STROBE INPUT RAS
LOWER BYTE CONTROL
COLUMN ADDRESS LCAS
STROBE INPUT
UPPER BYTE CONTROL UCAS
COLUMN ADDRESS
STROBE INPUT
WRITE CONTROL
INPUT
W
CLOCK GENERATOR
CIRCUIT
LOWER
UPPER
ADDRESS INPUTS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A0~A8
COLUMN DECODER
ROW &
COLUMN
ADDRESS
BUFFER
A0~ ROW
A8 DECODER
SENSE REFRESH
AMPLIFIER & I /O CONTROL
MEMORY CELL
(4194304 BITS)
(8)LOWER
DATA IN
BUFFER
(8)LOWER
DATA OUT
BUFFER
(8)UPPER
DATA IN
BUFFER
(8)UPPER
DATA OUT
BUFFER
2 M5M44260CJ,TP-5,-5S : Under development
VCC (5V)
VSS (0V)
DQ1
DQ2
DQ8
LOWER DATA
INPUTS /
OUTPUTS
VCC (5V)
VSS (0V)
DQ9
DQ10
DQ16
UPPER DATA
INPUTS /
OUTPUTS
VCC (5V)
VSS (0V)
OE
OUTPUT ENABLE
INPUT


Part Number M5M44260CJ-6S
Description FAST PAGE MODE 1M-Bit DRAM
Maker Mitsubishi
Total Page 29 Pages
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