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Mitsubishi
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M5M44800CJ-7 Datasheet Preview

M5M44800CJ-7 Datasheet

FAST PAGE MODE 4M-Bit DRAM

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M5M44800CJ-7 pdf
MITMSIUTBSIUSBHIISHLSI ILsSIs
M5MM5M444488000C0JC,TPJ-,5T,-6P,--75,-5,-S6,-,6-S7,-,7S
-5S,-6S,-7S
FAFSATSPTAPGAEGMEOMDOED4E19441390443-0B4I-TB(I5T2(45228482-8W8-OWRODRBDYB8Y-B8I-TB)IDT)YDNYANMAICMIRCARMAM
DESCRIPTION
This is a family of 524288-word by 8-bit dynamic RAMs, fabricated
with the high performance CMOS process, and is ideal for large-
capacity memory systems where high speed, low power
dissipation, and low costs are essential.
The use of double-layer metalization process technology and a
single-transistor dynamic storage stacked capacitor cell provide
high circuit density at reduced costs. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is low enough for
battery back-up application.
FEATURES
Type name
RAS CAS Address OE
access access access access
time time time time
Cycle
time
Power
dissipa-
tion
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
M5M44800CXX-5,-5S 50 13 25 13
90 450
M5M44800CXX-6,-6S 60 15 30 15 110 375
M5M44800CXX-7,-7S 70 20 35 20 130 325
XX=J,TP
Standard 28pin SOJ, 28pin TSOP (II)
Single 5V±10% supply
Low stand-by power dissipation
CMOS lnput level
5.5mW (Max)
CMOS Input level
550µW (Max) *
Operating power dissipation
M5M44800Cxx-5,-5S
495mW (Max)
M5M44800Cxx-6,-6S
413mW (Max)
M5M44800Cxx-7,-7S
358mW (Max)
Self refresh capability *
Self refresh current
150µA(Max)
Extended refresh capability
Extended refresh current
150µA(Max)
Fast page mode(1024-column random access),Read-modify-write,
RAS-only refresh, CAS before RAS refresh, Hidden refresh
capabilities.
Early-write mode, CAS and OE to control output buffer impedance
1024 refresh cycles every 16.4ms (A0 ~A9)
1024 refresh cycles every 128ms (A0 ~A9) *
* :Applicable to self refresh version (M5M44800CJ,TP-5S,-6S,-7S
:option) only
APPLICATION
Microcomputer memory, Refresh memory for CRT
PIN CONFIGURATION (TOP VIEW)
(5V)VCC 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
NC 6
W7
RAS 8
A9 9
A0 10
A1 11
A2 12
A3 13
(5V)VCC 14
28 VSS(0V)
27 DQ8
26 DQ7
25 DQ6
24 DQ5
23 CAS
22 OE
21 NC
20 A8
19 A7
18 A6
17 A5
16 A4
15 VSS(0V)
Outline 28P0K(400mil SOJ)
(5V)VCC 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
NC 6
W7
RAS 8
A9 9
A0 10
A1 11
A2 12
A3 13
(5V)VCC 14
28 VSS(0V)
27 DQ8
26 DQ7
25 DQ6
24 DQ5
23 CAS
22 OE
21 NC
20 A8
19 A7
18 A6
17 A5
16 A4
15 VSS(0V)
Outline 28P3Y-H(400mil TSOP Normal Bend)
NC:NO CONNECTION
PIN DESCRIPTION
Pin name
A0~A9
DQ1~DQ8
RAS
CAS
W
OE
Vcc
Vss
Function
Address inputs
Data inputs/outputs
Row address strobe input
Column address strobe input
Write control input
Output enable input
Power supply (+5V)
Ground (0V)
1
M5M44800CJ,TP-5,-5S:Under development



Mitsubishi
Mitsubishi

M5M44800CJ-7 Datasheet Preview

M5M44800CJ-7 Datasheet

FAST PAGE MODE 4M-Bit DRAM

No Preview Available !

M5M44800CJ-7 pdf
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
FUNCTION
In addition to normal read, write, and read-modify-write operations
the M5M44800CJ, TP provides a number of other functions, e.g.,
fast page mode, RAS-only refresh, and delayed-write. The input
conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Operation
Read
Write (Early write)
RAS
ACT
ACT
CAS
ACT
ACT
Inputs
W
NAC
ACT
OE
ACT
DNC
Row
address
APD
APD
Column
address
APD
APD
Write (Delayed write)
Read-modify-write
ACT
ACT
ACT
ACT
ACT
ACT
DNC
ACT
APD
APD
APD
APD
RAS only refresh
ACT
NAC
DNC DNC
APD
DNC
Hidden refresh
ACT
CAS before RAS (Extended *) refresh ACT
ACT
ACT
DNC
DNC
ACT
DNC
DNC
DNC
DNC
DNC
Self refresh *
ACT ACT
DNC DNC DNC DNC
Stand-by
NAC DNC
DNC DNC DNC DNC
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : invalid, APD : applied, OPN : open
Input/Output
Input
OPN
Output
VLD
VLD OPN
VLD IVD
VLD VLD
DNC
OPN
OPN
VLD
DNC
DNC
OPN
OPN
DNC OPN
Refresh Remark
YES
YES
YES
YES
YES
YES
YES
YES
NO
Fast page
mode
identical
BLOCK DIAGRAM
COLUMN ADDRESS
STROBE INPUT CAS
ROW ADDRESS RAS
STROBE INPUT
WRITE CONTROL W
INPUT
ADDRESS INPUTS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
CLOCK GENERATOR
CIRCUIT
A0~A8
COLUMN DECODER
ROW &
COLUMN
ADDRESS
BUFFER
A0~ ROW
A9 DECODER
SENSE REFRESH
AMPLIFIER & I /O CONTROL
MEMORY CELL
(4194304BITS)
2
M5M44800CJ,TP-5,-5S:Under development
(8)
DATA IN
BUFFER
(8)
DATA OUT
BUFFER
VCC (5V)
VCC (5V)
VSS (0V)
VSS (0V)
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DATA
INPUTS / OUTPUTS
OE OUTPUT ENABLE
INPUT


Part Number M5M44800CJ-7
Description FAST PAGE MODE 4M-Bit DRAM
Maker Mitsubishi
Total Page 21 Pages
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