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MH16D72AKLB-75 Datasheet Preview

MH16D72AKLB-75 Datasheet

1 /207.959 /552-BIT (16 /777 /216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

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MH16D72AKLB-75 pdf
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
DESCRIPTION
The MH16D72AKLB is 16777216 - word x 72-bit Double
Data Rate(DDR) Sy nchronous DRAM mounted module.
This consists of 9 industry standard 16M x 8 DDR
Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which
achiev es v ery high speed data rate up to 133MHz.
This socket-ty pe memory m odule is suitable f or main
memory in computer systems and easy to interchange or
add modules.
93pin 1pin
FEATURES
Type name
Max.
Frequency
MH16D72AKLB-75
MH16D72AKLB-10
133MHz
100MHz
CLK
Access Time
[component level]
+ 0.75ns
+ 0.8ns
- Utilizes industry standard 16M X 8 DDR Synchronous DRAMs
in TSOP package , industry standard Registered Buffer in
TSSOP package , and industry standard PLL in TSSOP package.
- Vdd=Vddq=2.5v ±0.2V
- Double data rate architecture; two data transf ers per
clock cy c le
- Bidirectional, data strobe (DQS) is transmitted/receiv ed
with data
- Dif f erential clock inputs (CK0 and /CK0)
- data and data mask ref erenced to both edges of DQS
- /CAS latency - 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Auto precharge / All bank precharge controlled by A10
- 4096 ref resh cy c les /64ms
- Auto ref resh and Self ref resh
- Row address A0-11 / Column address A0-9
- SSTL_2 Interf ace
- Module 1bank Conf igration
- Burst Ty pe - sequential/interleav e(programmable)
- Commands entered on each positiv e CLK edge
APPLICATION
Main memoryunit for PC, PCserver
144pin 52pin
145pin 53pin
184pin 92pin
MIT-DS-0397-1.1
MITSUBISHI ELECTRIC
24.Nov.2000
1



Mitsubishi
Mitsubishi

MH16D72AKLB-75 Datasheet Preview

MH16D72AKLB-75 Datasheet

1 /207.959 /552-BIT (16 /777 /216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

No Preview Available !

MH16D72AKLB-75 pdf
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16D72AKLB-10,75
,
1,207.959,552-BIT (16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
PIN CONFIGURATION
PIN PIN
PIN
NO. NAME NO.
PIN
NAME
1 VREF
2 DQ0
3 VSS
4 DQ1
5 DQS0
6 DQ2
7 VDD
8 DQ3
9 NC
10 RESET
11 VSS
12 DQ8
13 DQ9
14 DQS1
15 VDDQ
16 NC
17 NC
18 VSS
19 DQ10
20 DQ11
21 CKE0
22 VDDQ
43 A1
44 CB0
45 CB1
46 VDD
47 DQS8
48 A0
49 CB2
50 VSS
51 CB3
52 BA1
KEY
53 DQ32
54 VDDQ
55 DQ33
56 DQS4
57 DQ34
58 VSS
59 BA0
60 DQ35
61 DQ40
62 VDDQ
63 /WE
23 DQ16
24 DQ17
25 DQS2
64 DQ41
65 /CAS
66 VSS
26 VSS
67 DQS5
27 A9
68 DQ42
28 DQ28
29 A7
30 VDDQ
31 DQ19
32 A5
33 DQ24
34 VSS
35 DQ25
36 DQS3
37 A4
69 DQ43
70 VDD
71 NC
72 DQ48
73 DQ49
74 VSS
75 NC
76 NC
77 VDDQ
78 DQS6
38 VDD
79 DQ50
39 DQ26
40 DQ27
41 A2
42 VSS
80 DQ51
81 VSS
82 VDDID
83 DQ56
PIN
NO.
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
PIN
NAME
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
NC
NC
A13
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
NC
DQ20
A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
DQ23
VSS
A6
PIN PIN
NO. NAME
126 DQ28
127 DQ29
128 VDDQ
129 DM3
130 A3
131 DQ30
132 VSS
133 DQ31
134 CB4
135 CB5
136 VDDQ
137 CK0
138 /CK0
139 VSS
140 DM8
141 A10
142 CB6
143 VDDQ
144 CB7
KEY
145 VSS
146 DQ36
147 DQ37
148 VDD
149 DM4
150 DQ38
151 DQ39
152 VSS
153 DQ44
154 /RAS
155 DQ45
156 VDDQ
157 /S0
158 /S1
159 DM5
160 VSS
161 DQ46
162 DQ47
163 NC
164 VDDQ
165 DQ52
166 DQ53
PIN PIN
NO. NAME
167 NC
168 VDD
169 DM6
170 DQ54
171 DQ55
172 VDDQ
173 NC
174 DQ60
175 DQ61
176 VSS
177 DM7
178 DQ62
179 DQ63
180 VDDQ
181 SA0
182 SA1
183 SA2
184 VDDSPD
NC: Not Connected
MIT-DS-0397-1.1
MITSUBISHI ELECTRIC
24.Nov.2000
2


Part Number MH16D72AKLB-75
Description 1 /207.959 /552-BIT (16 /777 /216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
Maker Mitsubishi
Total Page 30 Pages
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