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MH28D72KLG-10 Datasheet Preview

MH28D72KLG-10 Datasheet

9 /663 /676 /416-BIT (134 /217 /728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

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MH28D72KLG-10 pdf
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
DESCRIPTION
The MH28D72KLG is 134217728 - word x 72-bit Double
Data Rate(DDR) Sy nchronous DRAM mounted module.
This consists of 36 industry standard 64M x 4 DDR
Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which
achiev es v ery high speed data rate up to 133MHz.
This socket-ty pe memory m odule is suitable f or main
memory in computer systems and easy to interchange or
add modules.
93pin 1pin
FEATURES
Type name
Max.
Frequency
MH28D72KLG-75
MH28D72KLG-10
133MHz
100MHz
CLK
Access Time
[component level]
+ 0.75ns
+ 0.8ns
- Utilizes industry standard 64M X 4 DDR Synchronous DRAMs
in TSOP package , industry standard Registered Buffer in
TSSOP package , and industry standard PLL in TSSOP package.
- Vdd=Vddq=2.5v ±0.2V
- Double data rate architecture; two data transf ers per
clock cy c le
- Bidirectional, data strobe (DQS) is transmitted/receiv ed
with data
- Dif f erential clock inputs (CLK and /CLK)
- data ref erenced to both edges of DQS
- /CAS latency - 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 ref resh cy c les /64ms
- Auto ref resh and Self ref resh
- Row address A0-12 / Column address A0-9,11
- SSTL_2 Interf ace
- Module 2bank Conf igration
- Burst Ty pe - sequential/interleav e(programmable)
- Commands entered on each positiv e CLK edge
APPLICATION
Main memoryunit for PC, PC server, Server, W S.
144pin 52pin
145pin 53pin
184pin 92pin
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
1



Mitsubishi
Mitsubishi

MH28D72KLG-10 Datasheet Preview

MH28D72KLG-10 Datasheet

9 /663 /676 /416-BIT (134 /217 /728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

No Preview Available !

MH28D72KLG-10 pdf
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
PIN CONFIGURATION
PIN PIN
PIN PIN
NO. NAME NO. NAME
1 VREF
2 DQ0
3 VSS
4 DQ1
5 DQS0
6 DQ2
7 VDD
8 DQ3
9 NC
10 RESET
11 VSS
12 DQ8
13 DQ9
14 DQS1
15 VDDQ
16 NC
17 NC
18 VSS
19 DQ10
20 DQ11
21 CKE0
22 VDDQ
43 A1
44 CB0
45 CB1
46 VDD
47 DQS8
48 A0
49 CB2
50 VSS
51 CB3
52 BA1
KEY
53 DQ32
54 VDDQ
55 DQ33
56 DQS4
57 DQ34
58 VSS
59 BA0
60 DQ35
61 DQ40
62 VDDQ
63 /WE
23 DQ16
64 DQ41
24 DQ17
65 /CAS
25 DQS2 66 VSS
26 VSS
67 DQS5
27 A9
68 DQ42
28 DQ18
69 DQ43
29 A7
70 VDD
30 VDDQ 71
NC
31 DQ19
72 DQ48
32 A5
73 DQ49
33 DQ24
74 VSS
34 VSS 75 NC
35 DQ25
76
NC
36 DQS3
77 VDDQ
37 A4
78 DQS6
38 VDD
79 DQ50
39 DQ26
40 DQ27
41 A2
42 VSS
80 DQ51
81 VSS
82 VDDID
83 DQ56
PIN PIN
PIN PIN
NO. NAME NO. NAME
84 DQ57 126 DQ28
85 VDD 127 DQ29
86 DQS7 128 VDDQ
87 DQ58 129 DQS12
88
DQ59
130
A3
89 VSS
131 DQ30
90 NC
132 VSS
91
SDA
133 DQ31
92
SCL
134 CB4
93
VSS
135 CB5
94
DQ4
136 VDDQ
95
DQ5
137 CK0
96
VDDQ
138
/CK0
97
DQS9
139
VSS
98 DQ6
140 DQS17
99 DQ7 141 A10
100 VSS 142 CB6
101 NC 143 VDDQ
102 NC 144 CB7
103 NC
KEY
104
VDDQ
145
VSS
105
DQ12
146
DQ36
106
DQ13
147
DQ37
107
DQS10
148
VDD
108
VDD
149 DQS13
109
DQ14
150
DQ38
110
DQ15
151
DQ39
111 CKE1 152 VSS
112
VDDQ
153
DQ44
113 NC 154 /RAS
114
DQ20
155
DQ45
115 A12 156 VDDQ
116 VSS 157 /S0
117
DQ21
158
/S1
118 A11
159 DQS14
119 DQS11 160
VSS
120 VDD
161 DQ46
121
DQ22
162
DQ47
122 A8 163 NC
123
DQ23
164
VDDQ
124 VSS 165 DQ52
125 A6 166 DQ53
PIN PIN
NO. NAME
167 NC
168 VDD
169 DQS15
170 DQ54
171 DQ55
172 VDDQ
173 NC
174 DQ60
175 DQ61
176 VSS
177 DQS16
178 DQ62
179 DQ63
180 VDDQ
181 SA0
182 SA1
183 SA2
184 VDDSPD
NC: No Connect
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
2


Part Number MH28D72KLG-10
Description 9 /663 /676 /416-BIT (134 /217 /728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
Maker Mitsubishi
Total Page 30 Pages
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