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Motorola Electronic Components Datasheet

MTD5P06V Datasheet

TMOS POWER FET

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTD5P06V/D
Designer's
TMOS V
Data Sheet
.
Power Field Effect Transistor
MTD5P06V
Motorola Preferred Device
DPAK for Surface Mount
P–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resis-
tance area product about one–half that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
D
New Features of TMOS V
On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than E–FET Predecessors
G
Features Common to TMOS V and TMOS E–FETS
Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS E–FET
Surface Mount Package Available in 16 mm, 13–inch/2500 Unit Tape & Reel,
Add –T4 Suffix to Part Number
TM
S
TMOS POWER FET
5 AMPERES
60 VOLTS
RDS(on) = 0.450 OHM
CASE 369A–13, Style 2
DPAK Surface Mount
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 M)
Gate–to–Source Voltage — Continuous
Gate–to–Source Voltage — Non–repetitive (tp 10 ms)
Drain Current — Continuous @ 25°C
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp 10 µs)
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
60
60
± 15
± 25
5
4
18
40
0.27
2.1
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — STARTING TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, PEAK IL = 5 Apk, L = 10 mH, RG = 25 )
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8from Case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
TJ, Tstg
EAS
RθJC
RθJA
RθJA
TL
– 55 to 175
125
3.75
100
71.4
260
°C
mJ
°C/W
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
© MMoototororloa,laIncT.M19O96S Power MOSFET Transistor Device Data
1


Motorola Electronic Components Datasheet

MTD5P06V Datasheet

TMOS POWER FET

No Preview Available !

MTD5P06V pdf
MTD5P06V
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
Gate–Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 2.5 Adc)
Drain–Source On–Voltage
(VGS = 10 Vdc, ID = 5 Adc)
(VGS = 10 Vdc, ID = 2.5 Adc, TJ = 150°C)
Forward Transconductance
(VDS = 15 Vdc, ID = 2.5 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
(VDD = 30 Vdc, ID = 5 Adc,
VGS = 10 Vdc,
RG = 9.1 )
Gate Charge
(See Figure 8)
(VDS = 48 Vdc, ID = 5 Adc,
VGS = 10 Vdc)
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 5 Adc, VGS = 0 Vdc)
(IS = 5 Adc, VGS = 0 Vdc, TJ = 150°C)
Reverse Recovery Time
(IS = 5 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25from package to source bond pad)
(1) Pulse Test: Pulse Width 300 µs, Duty Cycle 2%.
(2) Switching characteristics are independent of operating junction temperature.
V(BR)DSS
IDSS
IGSS
VGS(th)
RDS(on)
VDS(on)
gFS
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
VSD
trr
ta
tb
QRR
LD
LS
60
2.0
1.5
Vdc
——
61.2 — mV/°C
µAdc
— 10
— 100
— 100 nAdc
Vdc
2.8 4.0
4.7 — mV/°C
0.34 0.45 Ohm
Vdc
— 2.7
— 2.6
Mhos
3.6 —
367 510 pF
140 200
29 60
11 20 ns
26 50
17 30
19 40
12 20 nC
3.0 —
5.0 —
5.0 —
Vdc
1.72 3.5
1.34 —
97 — ns
73 —
24 —
0.42 —
µC
nH
4.5 —
nH
7.5 —
2 Motorola TMOS Power MOSFET Transistor Device Data


Part Number MTD5P06V
Description TMOS POWER FET
Maker Motorola
Total Page 10 Pages
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