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  NEC Electronic Components Datasheet  

80N055 Datasheet

NP80N055

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80N055 pdf
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
NP80N055CLE, NP80N055DLE, NP80N055ELE
SWITCHING
N-CHANNEL POWER MOS FET
INDUSTRIAL USE
DESCRIPTION
These products are N-channel MOS Field Effect
www.DataSheet4UT.rcaonmsistor designed for high current switching
applications.
FEATURES
Channel temperature 175 degree rated
Super low on-state resistance
RDS(on)1 = 11 mMAX. (VGS = 10 V, ID = 40 A)
RDS(on)2 = 13 mMAX. (VGS = 5 V, ID = 40 A)
Low Ciss : Ciss = 2900 pF TYP.
Built-in gate protection diode
ORDERING INFORMATION
PART NUMBER
NP80N055CLE
NP80N055DLE
NP80N055ELE
PACKAGE
TO-220AB
TO-262
TO-263
(TO-220AB)
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage
VDSS
55
Gate to Source Voltage
Drain Current (DC) Note1
Drain Current (Pulse) Note2
VGSS
ID(DC)
ID(pulse)
±20
±80
±200
Total Power Dissipation (TA = 25 °C)
PT
1.8
Total Power Dissipation (TC = 25 °C)
Single Avalanche Current Note3
Single Avalanche Energy Note3
PT
IAS
EAS
120
45 / 30 / 10
2.0 / 90 / 100
Channel Temperature
Tch 175
Storage Temperature
Tstg –55 to +175
V
V
A
A
W
W
A
mJ
°C
°C
Notes 1. Calculated constant current according to MAX. allowable channel
temperature.
2. PW 10 µs, Duty cycle 1 %
3. Starting Tch = 25 °C, RG = 25 , VGS = 20 V0 V (see Figure 4.)
THERMAL RESISTANCE
Channel to Case
Rth(ch-C)
1.25 °C/W
Channel to Ambient
Rth(ch-A)
83.3 °C/W
(TO-262)
(TO-263)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. D14097EJ3V0DS00 (3rd edition)
Date Published March 2001 NS CP(K)
Printed in Japan
The mark 5 shows major revised points.
©
1999,2000


  NEC Electronic Components Datasheet  

80N055 Datasheet

NP80N055

No Preview Available !

80N055 pdf
NP80N055CLE, NP80N055DLE, NP80N055ELE
ELECTRICAL CHARACTERISTICS (TA = 25 °C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Drain to Source On-state Resistance
RDS(on)1 VGS = 10 V, ID = 40 A
RDS(on)2 VGS = 5 V, ID = 40 A
RDS(on)3 VGS = 4.5 V, ID = 40 A
Gate to Source Threshold Voltage
VGS(th) VDS = VGS, ID = 250 µA
Forward Transfer Admittance
| yfs | VDS = 10 V, ID = 40 A
Drain Leakage Current
IDSS VDS = 55 V, VGS = 0 V
Gate to Source Leakage Current
IGSS VGS = ±20 V, VDS = 0 V
Input Capacitance
www.DataSheet4U.com
Output Capacitance
Ciss
Coss
VDS = 25 V, VGS = 0 V, f = 1 MHz
Reverse Transfer Capacitance
Crss
Turn-on Delay Time
td(on)
ID = 40 A, VGS(on) = 10 V, VDD = 28 V,
Rise Time
tr RG = 1
Turn-off Delay Time
td(off)
Fall Time
tf
Total Gate Charge 1
QG1 ID = 80 A, VDD = 44 V, VGS = 10 V
Total Gate Charge 2
QG2 ID = 80 A, VDD = 44 V, VGS = 5 V
Gate to Source Charge
QGS
Gate to Drain Charge
QGD
Body Diode Forward Voltage
VF(S-D) IF = 80 A, VGS = 0 V
Reverse Recovery Time
trr IF = 80 A, VGS = 0 V, di/dt = 100 A/µs
Reverse Recovery Charge
Qrr
MIN. TYP. MAX. UNIT
8.4 11 m
10.3 13 m
11.3 15 m
1.5 2.0 2.5 V
20 40
S
10 µA
±10 µA
2900 4400 pF
380 570 pF
170 310 pF
22 48 ns
10 25 ns
62 120 ns
11 27 ns
50 75 nC
26 39 nC
12 nC
15 nC
1.0 V
50 ns
100 nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25
PG.
VGS = 20 0 V
50
L
VDD
ID
VDD
IAS
BVDSS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = 2 mA
PG. 50
RL
VDD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
PG. RG
VGS
0
τ
τ = 1 µs
Duty Cycle 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VDS
90%
VDS
VDS
Wave Form
0
td(on)
90%
VGS(on)
90%
10% 10%
tr td(off)
tf
ton toff
2 Data Sheet D14097EJ3V0DS


Part Number 80N055
Description NP80N055
Maker NEC
Total Page 8 Pages
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