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  NEC Electronic Components Datasheet  

D4701A Datasheet

UPD4701A

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D4701A pdf
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4701A
INCREMENTAL ENCODER COUNTER
DESCRIPTION
The µPD4701A is a counter for an X, Y 2-axis incremental encoder. When a two-phase encoder signal is input
for the X and Y axes, direction discrimination and computation is performed, and count data is output in 8-bit parallel
form. In addition, a 3-contact-point input buffer is incorporated, which is useful for applications which use a pointing
device such as a mouse or track-ball. The CPU checks the switch input flag or count flag and reads the 12-bit count
data in two operations, one for the lower byte and one for the upper byte. The key input flag is output together with
the count data in the upper byte.
FEATURES
• X, Y 2-axis incremental encoder counter
• Counter input (Schmitt-triggered input)
X axis:
Y axis:
XA,
YA,
XB
YB
2-phase
2-phase
signal
signal

4-multiplication
count
method
used
• Counters: 12-bit binary up/down counters (2 sets, X & Y)
Reset value: 000H
• Count data output: 8-bit parallel latch output × 2 (including key input flag)
• On-chip 3-contact-point key input buffer circuit
• CMOS
• Single +5 V power supply
PIN CONFIGURATION (Top View)
PIN NAMES
XA, YA : A-phase inputs
XB, YB : B-phase inputs
RIGHT
LEFT Key inputs
MIDDLE
XA
XB
RESET X
YA
1
2
3
4
24 VDD
23 D7
22 D6
21 D5
CS
X/Y
U/L
D0 to 7
CF
SF
: Chip Select
: X/Y Counter Select
: Upper/Lower Byte Select
: Data outputs
: Count flag
: Count flag
RESET
RESET
X
Y

Counter
reset inputs
YB
RESET Y
RIGHT
LEFT
MIDDLE
SF
5
6
7
8
9
10
20 D4
19 D3
18 D2
17 D1
16 D0
15 CS
CF 11
14 X/Y
VSS 12
13 U/L
wwwD(O.Do.caDutm.aSNehnoet. eNtICo4U.-6.I9nC4e-7t3A3)03 (1st edition)
Date Published March 1997 P
Printed in Japan
© 1993


  NEC Electronic Components Datasheet  

D4701A Datasheet

UPD4701A

No Preview Available !

D4701A pdf
µPD4701A
ORDERING INFORMATION
Part Number
µPD4701AC
µPD4701AGT
Package
24-pin plastic DIP (600 mil)
24-pin plastic SOP (375 mil)
BLOCK DIAGRAM
XA
XB
RESET X
Phase
Determination
and
Edge Detection
X-Axis Up/Down Counter
Data Multiplexer & Latch
RESET Y
YA
YB
Phase
Determination
and
Edge Detection
RIGHT
LEFT
MIDDLE
Button Input
Circuit
DATA MULTIPLEXER/LATCH BLOCK
Y-Axis Up/Down Counter
Count Flag
Circuit
Switch Flag
Circuit
CS
X/Y
U/L
D0-7
CF
SF
X-Axis Counter
12-Bit
Latch
STB
8
X/Y
U/L
Y-Axis Counter
12-Bit
Latch
STB
8
Data
8
Multiplexer
4
3-State
Buffer
OE
D0 - 7
Button Input
4-Bit
Latch
STB
CS
To Count Flag Circuit
2


Part Number D4701A
Description UPD4701A
Maker NEC
Total Page 16 Pages
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